• Title/Summary/Keyword: Module design

Search Result 4,023, Processing Time 0.033 seconds

A Design and Implementation of WML Compiler for WAP Gateway for Wireless Internet Services (무선 인터넷 서비스를 위한 WAP 게이트웨이용 WML 컴파일러의 설계 및 구현)

  • Choi, Eun-Jeong;Han, Dong-Won;Lim, Kyung-Shik
    • Journal of KIISE:Computing Practices and Letters
    • /
    • v.7 no.2
    • /
    • pp.165-182
    • /
    • 2001
  • In this paper, we describe a design and implementation of the Wireless Markup Language(WML) compiler to deploy wireless Internet services effectively. The WML compiler translates textual WML decks into binary ones in order to reduce the traffic on wireless links that have relatively low bandwidth to wireline links and mitigate the processing overhead of WML decks on, wireless terminals that have relatively low processing power to fixed workstations. In addition, it takes over the overhead of eXtensible Markup Language(XML) well-formedness and validation processes. The WML compiler consists of the lexical analyzer and parser modules. The granunar for the WML parser module is LALR(1) context-free grammar that is designed based on XML 1.0 and WML 1.2 DTD(Document Type Definition) with the consideration of the Wireless Application Protocol Binary XML grammar. The grammar description is converted into a C program to parse that grammar by using parser generator. Even though the tags in WML will be extended or WML DTD will be upgraded, this approach has the advantage of flexibility because the program is generated by modifying just the changed parts. We have verified the functionality of the WML compiler by using a WML decompiler in the public domain and by using the Nokia WAP Toolkit as a WAP client. To measurethe compressibility gain of the WML compiler, we have tested a large number of textual WML decks and obtained a maximum 85 %. As the effect of compression is reduced when the portion of general textual strings increases relative to one of the tags and attributes in a WML deck, an extended encoding method might be needed for specific applications such as compiling of the WML decks to which the Hyper Text Markup Language document is translated dynamically.

  • PDF

Study on the Performance Verification of PRB Isolation Device using Simulation and Experiment (PRB 지진격리장치의 성능 검증을 위한 해석 및 실험적 연구)

  • Kim, Sung-Jo;Kim, Se-Yun;Ji, Yongsoo;Kim, Bongsik;Han, Tong-Seok
    • Journal of the Computational Structural Engineering Institute of Korea
    • /
    • v.33 no.5
    • /
    • pp.311-318
    • /
    • 2020
  • This study introduces a technique for improving the elastomeric-isolator performance using modular devices. The modular devices are shear resistance block, polymer spring, displacement acceptance guide, and anti-falling block. They are installed on the elastomeric isolator as a supplementary device. Each modularized device improves the isolator performance by performing step-by-step actions according to the seismic intensity and displacement. The PRB isolation device works in four stages, depending on the seismic magnitude, to satisfy the target performance. It is designed to accommodate design displacement in the first stage and large magnitude of earthquakes in the second and third stages. This design prevents superstructures from falling in the fourth stage due to large-magnitude earthquakes by increasing the capacity limit of the elastomeric isolator. In this study, the PRB isolation device is analyzed using finite element analysis to verify that the PRB isolation device works as intended and it can withstand loads corresponding to large-magnitude earthquakes. The performance of the PRB isolation device is validated by the analysis, which is further corroborated by actual experiments.

A Study on Evaluation of Floor Vibration for Steel Frame Modular Housing (철골 조립식주택 바닥판 진동 평가에 관한 연구)

  • Kim, Jong-Sung;Jo, Min-Joo;Kim, Seung-Hun
    • Journal of the Korea institute for structural maintenance and inspection
    • /
    • v.20 no.1
    • /
    • pp.104-111
    • /
    • 2016
  • The steel frame modular housing of which the research and development has been actively carried out recently cannot be constructed through monolithic placement like the reinforced concrete deck of general structure due to the characteristics of construction method of production in the factory and assembly on the site. And floor vertical vibration and deflection caused by inhabitants' activities may become an important issue in the aspect of usability evaluation due to a decrease in the section size of member, a decrease in weight, and so on. Therefore, this study evaluated the vibration performance of deck by using formula of AISC Design Guide 11(hereinafter AISC formula) which was practically used in general for modules where a stud was and wasn't installed at the center of beam in the longitudinal direction in the modular housing to be studied, and examined the applicability of AISC formula through comparison with the results of analysis using a general-purpose analysis program. On the basis of this, a structural cause for an error to occur between analysis result and AISC formula in the deck of module in which a stud was installed was analysed, and measures for considering this were suggested. Besides, an analysis model with the variables of measures for improving the floor vibration performance of modular housing to be studied was established. And measures having excellent vibration performance and economic feasibility were suggested through vibration response analysis and economic evaluation.

IGRINS First Light Instrumental Performance

  • Park, Chan;Yuk, In-Soo;Chun, Moo-Young;Pak, Soojong;Kim, Kang-Min;Pavel, Michael;Lee, Hanshin;Oh, Heeyoung;Jeong, Ueejeong;Sim, Chae Kyung;Lee, Hye-In;Le, Huynh Anh Nguyen;Strubhar, Joseph;Gully-Santiago, Michael;Oh, Jae Sok;Cha, Sang-Mok;Moon, Bongkon;Park, Kwijong;Brooks, Cynthia;Ko, Kyeongyeon;Han, Jeong-Yeol;Nah, Jakyuong;Hill, Peter C.;Lee, Sungho;Barnes, Stuart;Park, Byeong-Gon;T., Daniel
    • The Bulletin of The Korean Astronomical Society
    • /
    • v.39 no.1
    • /
    • pp.52.2-52.2
    • /
    • 2014
  • The Immersion Grating Infrared Spectrometer (IGRINS) is an unprecedentedly minimized infrared cross-dispersed echelle spectrograph with a high-resolution and high-sensitivity optical performance. A silicon immersion grating features the instrument for the first time in this field. IGRINS will cover the entire portion of the wavelength range between 1.45 and $2.45{\mu}m$ accessible from the ground in a single exposure with spectral resolution of 40,000. Individual volume phase holographic (VPH) gratings serve as cross-dispersing elements for separate spectrograph arms covering the H and K bands. On the 2.7m Harlan J. Smith telescope at the McDonald Observatory, the slit size is $1^{\prime\prime}{\times}15^{\prime\prime}$. IGRINS has a $0.27^{\prime\prime}$ pixel-1 plate scale on a $2048{\times}2048$ pixel Teledyne Scientific & Imaging HAWAII-2RG detector with SIDECAR ASIC cryogenic controller. The instrument includes four subsystems; a calibration unit, an input relay optics module, a slit-viewing camera, and nearly identical H and K spectrograph modules. The use of a silicon immersion grating and a compact white pupil design allows the spectrograph collimated beam size to be 25mm, which permits the entire cryogenic system to be contained in a moderately sized rectangular vacuum chamber. The fabrication and assembly of the optical and mechanical hardware components were completed in 2013. In this presentation, we describe the major design characteristics of the instrument and the early performance estimated from the first light commissioning at the McDonald Observatory.

  • PDF

Design of 77 GHz Automotive Radar System (77 GHz 차량용 레이더 시스템 설계)

  • Nam, Hyeong-Ki;Kang, Hyun-Sang;Song, Ui-Jong;Cui, Chenglin;Kim, Seong-Kyun;Nam, Sang-Wook;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.24 no.9
    • /
    • pp.936-943
    • /
    • 2013
  • This work presents the design and measured results of the single channel automotive radar system for 76.5~77 GHz long range FMCW radar applications. The transmitter uses a commercial GaAs monolithic microwave integrated circuit(MMIC) and the receiver uses the down converter designed using 65 nm CMOS process. The output power of the transmitter is 10 dBm. The down converter chip can operate at low LO power as -8 dBm which is easily supplied from the transmitter output using a coupled line coupler. All MMICs are mounted on an aluminum jig which embeds the WR-10 waveguide. A microstrip to waveguide transition is designed to feed the embedded waveguide and finally high gain horn antennas. The overall size of the fabricated radar system is $80mm{\times}61mm{\times}21mm$. The radar system achieved an output power of 10 dBm, phase noise of -94 dBc/Hz at 1 MHz offset and a conversion gain of 12 dB.

Image Generator Design for OLED Panel Test (OLED 패널 테스트를 위한 영상 발생기 설계)

  • Yoon, Suk-Moon;Lee, Seung-Ho
    • Journal of IKEEE
    • /
    • v.24 no.1
    • /
    • pp.25-32
    • /
    • 2020
  • In this paper, we propose an image generator for OLED panel test that can compensate for color coordinates and luminance by using panel defect inspection and optical measurement while displaying images on OLED panel. The proposed image generator consists of two processes: the image generation process and the process of compensating color coordinates and luminance using optical measurement. In the image generating process, the panel is set to receive the panel information to drive the panel, and the image is output by adjusting the output setting of the image generator according to the panel information. The output form of the image is configured by digital RGB method. The pattern generation algorithm inside the image generator outputs color and gray image data by transmitting color data to a 24-bit data line based on a synchronization signal according to the resolution of the panel. The process of compensating color coordinates and luminance using optical measurement outputs an image to an OLED panel in an image generator, and compensates for a portion where color coordinates and luminance data measured by an optical module differ from reference data. To evaluate the accuracy of the image generator for the OLED panel test proposed in this paper, Xilinx's Spartan 6 series XC6SLX25-FG484 FPGA was used and the design tool was ISE 14.5. The output of the image generation process was confirmed that the target setting value and the simulation result value for the digital RGB output using the oscilloscope matched. Compensating the color coordinates and luminance using optical measurements showed accuracy within the error rate suggested by the panel manufacturer.

Optical Design of an Integrated Two-Channel Optical Transmitter for an HDMI interface (광 HDMI 인터페이스용 2채널 광송신기 광학 설계)

  • Yoon, Hyun-Jae;Kang, Hyun-Seo
    • Korean Journal of Optics and Photonics
    • /
    • v.26 no.5
    • /
    • pp.269-274
    • /
    • 2015
  • In this paper we design the optical system for an integrated two-channel TO-type optical transmitter to apply the HDMI interface using the code V simulator. The proposed integrated two-channel optical transmitter has two VCSELs attached in parallel on an 8-pin TO-CAN package, on top of which is a lens filter block ($1mm{\times}2mm{\times}4mm$) composed of hemispherical lenses and WDM filters. Considering two-channel transmitters manufactured with wavelength combinations of 1060nm/1270nm and 1330nm/1550nm, we obtain the optimum value of the diameter of the hemispherical lens as 0.6 mm for both combinations, and the distances L between the lens filter block and ball lens as 1.7 mm and 2.0 mm for the 1060nm/1270nm and 1330nm/1550nm wavelength combinations, respectively. At this time, the focal length f0 of the lens filter blocks for wavelengths of 1060, 1270, 1330, and 1550 nm are 0.351, 0.354, 0.355, and 0.359 mm, respectively, and the focal lengths F of light passing through the lens filter block and ball lens are 0.62 mm for 1060nm/1270nm and 0.60-0.66 mm for 1330nm/1550nm wavelength combinations.

An evaluation of the composition and elements in Korean traditional interior space - On Choosa-Gotack in the Chosun dynasty - (한국전통 실내공간의 구성방법과 요소 분석을 통한 의미 고찰 - 조선조 추사고택을 중심으로 -)

  • 천진희
    • Archives of design research
    • /
    • no.16
    • /
    • pp.101-110
    • /
    • 1996
  • CHOOSA GORACK which is a typical example of traditional houses in the CHO SEON dynasty consists of the four terraced builfing group. Among those,SADANG CHAI are located in the highest level,and SADANG CHAI and SADANG CHAI are toward south direction.It means that building orientation and level were influenced by the distinction of social level and the idea of ancester worship. Floor and ceiling level in the same building is different which was caused by the distinetion of social level in the CHO SEON dynasty and an ariental dual as a variety of openings,exposed ceilings,and furniture against a wall were creating a typical Korean visual harmony. Although the furniture and equipments were very important elements in ONDOL BANG the occupance ratio of these were low because the free space in BANG should be utilized effectively to accommodate the space variation.Both an AN CHAI and SARANG CHAI were composed by the standard space module called KAN.And interior elements were established by several factors such as the human scale,the behavior pattern in traditional sitting life style, and the lumber size of post and lintel construction of Korean house.BANG and DAE GHUNG, composed of KAN,were expanded and arranged side by side so that the natural light and ventilation through them could be used in the result of the kind of lay out,traffic circulation was disturved.In conclusion,CHOOSA GOTACK was formed by the sirect effice of the KOREAN penisula. However this study was based on one sample. It may not enough to deduct soild conclusion.Therefore continuous and farher study is needed for the sestemane evaluation.

  • PDF

A study on development of RGB color variable optical ID module considering smart factory environment (스마트 팩토리 환경을 고려한 RGB 컬러 가변형 광 ID 모듈개발 연구)

  • Lee, Min-Ho;Timur, Khudaybergenov;Lee, Beom-Hee;Cho, Ju-Phil;Cha, Jae-Sang
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
    • /
    • v.11 no.5
    • /
    • pp.623-629
    • /
    • 2018
  • Smart Factory is a concept of automatic production system of machines by the fusion of ICT and manufacturing. As a base technology for realizing such a smart factory, there is an increasing interest in a low-power environmentally friendly LED lighting system, and researches on so-called optical ID related application technologies such as communication using a LED and position recognition are actively underway. In this paper, We have proposed a system that can reliably identify logistics location and additional information without being affected by electromagnetic interference such as high voltage, high current, and generator in the plant. Through the basic experiment, we confirmed the applicability of the color ID recognition rate from 98.8% to 93.8% according to the eight color variations in the short distance.

Hardware Design of High Performance HEVC Deblocking Filter for UHD Videos (UHD 영상을 위한 고성능 HEVC 디블록킹 필터 설계)

  • Park, Jaeha;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.19 no.1
    • /
    • pp.178-184
    • /
    • 2015
  • This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.