• Journal of Internet Computing and Services
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• v.10 no.4
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• pp.139-149
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• 2009

In order to verify that a lot of legal requirements and regulations are correctly translated into software, this paper provides a solution for formal and computable representations of rules and requirements in data protection legislations with a DSML (Domain Specific Modeling Language). All policies are formally specified through Prolog and then integrated with DSML, According to the time of policy verification, this solution has two kinds of policies: static policies, dynamic policies.

• Plant Journal
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• v.13 no.2
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• pp.39-45
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• 2017

This paper is a study on FEED validation model that can be used in the bidding stage of small utility equipment in offshore plant industry using system engineering technique. Currently, domestic marine plant equipment industry companies are faced with the financial risk of project execution as they enter marine plant. The major cause was the insufficient ability to verify the FEED output from the contractor (Engineering or Procurement and Construction) of the equipment manufacturer (COMPANY or EPC). Therefore, we propose FEED design verification method that simplifies the system engineering method that sequentially applies requirements analysis, function, performance analysis and physical architecture building process. Also, we verified the suitability of the developed model by comparing the results of applying the developed FEED verification model and the verification method that depends on the existing experience for the small utility equipment (Air Compressor).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.43-52
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• 2004

This paper proposes an efficient functional verification environment of microprocessor. This verification environment consists of test vector generator part, simulator part, and comparator part. To enhance efficiency of verification, it use a bias random test vector generator. In a part of simulation, retargetable instruction level simulator is used for reference model. This verification environment is excellent to find error which is not detected by general test vector and will become a good guide to find new error type

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.409-416
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• 1996

This paper describes the simulation environment that verifies whether a new microporcessor described with HDL is compatible with an existing microprocessor. The compatibility verification is done by showing that the new microprocessor executes the OS(Operating System) program used in the existing microprocessor without any modification of its binary code. The proposed verification environment consists of a virtual system and a graphic user interface (GUI) module. Each module is independently designed based on serve-client model and three exists a communication part for information interchange between the two modules. This paper describes the method of constructing the verification environment and presents the compatibility verification environment of the x86 microprocessor as the simulation result.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.11a
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• pp.109-110
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• 2007

• Journal of the Korean Society for Precision Engineering
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• v.22 no.4
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• pp.68-75
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• 2005

This paper presents a new method for the optimization of feed rate in sculptured surface machining. A NC verification model based on Z-map was utilized to obtain chip load according to feed per tooth. This optimization method can regenerate a new NC program with respect to the commanded cutting conditions and the NC program that was generated from CAM system. The regenerated NC program has not only the same data of the ex-NC program but also the updated feed rate in every block. The new NC data can reduce the cutting time and produce precision products with almost even chip load to the feed per tooth. This method can also reduce tool chipping and make constant tool wear.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.6 no.1
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• pp.51-58
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• 1997

The verification of the STL file is essential to build the confident parts using a RP machine, because the STL file obtained from the CAD software has many errors-the orientation of triangle does not coincide with adjacent triangles or some triangles are omitted, overlpped and so forth. Especially, the STL file translated from the surface model has more errors than those translated from the solid model. In this study, all possible errors were classified with the most general from and the causes of errors were analyzed to verify and correct errors. Using the triangle based non-manifold geometric modeling, these errors were corrected. Especially, this study took the notice of the problem about the intersected triangles and non-manifold properties overlooked in the previous studies. But this study has a penalty on computing time of $O(n^2)$.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.947-954
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• 2014

Performance of next generation susceptor is affected by temperature uniformity in order to produce reliably large-sized flat panel display. In this paper, we propose a learning estimation model of susceptor to predict and appropriately assess the temperature uniformity. Artificial Neural Networks (ANNs) and Support Vector Machines (SVMs) are compared for the suitability of the learning estimation model. It is proved that SVMs provides more suitable verification of uniformity modeling than ANNs during each stage of temperature variations. Practical procedure for uniformity estimation of susceptor temperature was developed using the SVMs prediction algorithm.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.801-805
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• 2000

This paper presents a new method of tool path optimization. A NC verification model based Z-map was utilized to obtain chip load in feed per tooth. This developed software can regenerate a NC program from cutting condition and the NC program that was generated in CAM. The regenerated NC program has not only all same data of the ex-NC program but also the new feed rates in every block. The new NC data can reduce the cutting time and manufacture precision dies with the same chip load in feed per tooth. This method can also prevent tool chipping and make constant tool wear. This paper considered the effects of acceleration and deceleration in feed rate change.