• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.341-350
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• 2016

The current study is dedicated to design a novel coordinated controller to effectively increase power system rotor angle stability. In doing so, the coordinated design of an AVR (automatic voltage regulator), PSS2B, and TCSC (thyristor controlled series capacitor)-based POD (power oscillation damping) controller is proposed. Although the recently employed coordination between a CPSS (conventional power system stabilizer) and a TCSC-based POD controller has been shown to improve power system damping characteristics, neglecting the negative impact of existing high-gain AVR on the damping torque by considering its parameters as given values, may reduce the effectiveness of a CPSS-POD controller. Thus, using a technologically viable stabilizer such as PSS2B rather than the CPSS in a coordinated scheme with an AVR and POD controller can constitute a well-established design with a structure that as a high potential to significantly improve the rotor angle stability. The design procedure is formulated as an optimization problem in which the ITSE (integral of time multiplied squared error) performance index as an objective function is minimized by employing an IPSO (improved particle swarm optimization) algorithm to tune adjustable parameters. The robustness of the coordinated designs is guaranteed by concurrently considering some operating conditions in the optimization process. To evaluate the performance of the proposed controllers, eigenvalue analysis and time domain simulations were performed for different operating points and perturbations simulated on 2A4M (two-area four-machine) power systems in MATLAB/Simulink. The results reveal that surpassing improvement in damping of oscillations is achieved in comparison with the CPSS-TCSC coordination.

• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.24-27
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• 2016

In this study, a 1kW Solid Oxide Fuel Cell(SOFC) test system was developed. A SOFC is the most promising power system to provide the higher efficient(over 50%) for house application area(1~10kW). To develop the optimized test system, the temperature control module that controls the preprocess and reaction condition, the flow control module that controls of the mass of reactants, and the electric loader that tests the discharge performance condition, etc. The temperature control module was designed to provide the high control resolution(under $1^{\circ}C$ at $750^{\circ}C$ of operating temperature) using K-type thermal couple. The flow control module was designed control blower and heater precisely using the phase control method. And the electric loader is designed that provide CV, CC, CR discharge mode and minimized the operating error adopting the independent DC-DC converter on analog input and output module. The performance of the developed SOFC test system showed that the accuracy of stack voltage was 0.15% at 80V and stack current was 0.1% at 100A.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.