• 한국정밀공학회지
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• 제1권2호
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• pp.69-74
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.

• 대한전기학회논문지
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• 제33권2호
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• pp.62-69
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2900 "bit-slice" microprocessor chips and 0.5K ROMs of 36-bit microprogram memory. The system design is an instuction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolation speed of 250 K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software, and experimental results are presented.presented.

• ETRI Journal
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• 제26권6호
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 하계종합학술대회 논문집
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• pp.134-137
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• 1989

A digital controller for a discrete-data control system can take many forms. For example, they can be passive RC networks, general purpose digital computers, special purpose of mini-computer, and delay lines. With the recent advent of the microprocessor, its use as a digital controller is evident. This work discusses the hardware and software development of a microprocessor-based digital controller for a discrete-data control system. A second-order, Type 1 system is implemented on an analog computer; a Intel 80-286 microprocessor is used to implemented the controller; and, output response are obtained for step, ramp, and parabolic inputs. The results demonstrate that the microprocessor has potential as a digital controller. Finally, a brief discussion on the results indicate possible areas of improvement of the controller and future investigation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 하계학술대회 논문집
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• pp.413-417
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• 1990

Various sampling methods are used for microprocessor-based measurement and analysis to nonsinusoidal waveforms caused by power electronic converters. The hamonic component generates the indicating errors at the measuring instruments. This can be solved by microprocessor-based measurement and hence the microprocessor-based measuring equipment and its algorithm are developed in this paper. As a result the suggested equipment has very good measuring performances.

• 조명전기설비학회논문지
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• 제19권8호
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• pp.109-115
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• 2005

이 논문은 자동차에서 제어 네트워크로 이미 신뢰성이 확인된 CAN(Controller Area Network) 필드버스를 산업계 복수전동기 제어에 적용하기 위하여 지능형 제어모듈로 CAN이 내장된 DSP2812 프로세서를 이용하여 제어 및 모니터링기술을 개발하였다. 산업계에 광범위하게 사용되고 있는 유도전동기를 대상으로 여러 대의 유도전동기를 제어하기 위한 제어 알고리즘과 CAN 기반제어네트워크 구축방법을 개발하였다. 이 시스템 성능을 평가하기 위하여 2대의 유도전동기 인버터 구동시스템에 적용하여 CAN 기반 네트워크 제어 실험을 수행하였다. 그 결과 광범위한 속도와 정역회전에서 실시간 네트워크 기반 제어성능을 확인하였다.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제2B권4호
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• pp.207-213
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• 2002

The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

• 대한전자공학회논문지
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• 제16권3호
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• pp.19-27
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• 1979

디지탈 필타를 마이크로프로세서를 이용하여 설계하였다. 포커스 수를 사용하여 수를 표시하므로서 승제산을 고속화하였고, 가감산은 환산표를 활용하여 처리하였다. 이리하여 삼차의 저역통과 디지탈 필타의 샘플이 500 (samples/sec)까지 처리 되었다.

• 품질경영학회지
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• 제28권1호
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• pp.27-40
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• 2000

Technological forecasting for microprocessor market can provide timely insight into the prospects for significant technological changes in computer hardware as well as software. In this paper, we use bibliometrics to forecast R&D trend on microprocessor technology. Cumulative numbers of US Patents on several generations of microprocessor technology (pipeline, superpipeline, supersclar and VLIW) approved since 1980 are applied to fit diffusion models. Our study results provide both the maximum market potential and the maturity time for each generation of microprocessor technology. Such information is expected to make contribution on making better decisions with regard to strategic corporate planning, R&D management, product development and investment in new technology of microprocessor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.408-411
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• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.