• The KIPS Transactions:PartD
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• v.15D no.2
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• pp.213-222
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• 2008

The existing approaches for the music application have not considered a real-time multi-tasking model. So, it suffers from a high complexity and a low flexibility in design as well as lack of predictability for the timely execution of critical tasks. In this paper, we design a new concurrent tasking architecture for a real-time embedded music system and examine if all real-time tasks can finish execution within their respective time constraints. The design is implemented on the Linux based Xhyper272 Board that uses the Intel Bulverde microprocessor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2015-2021
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• 2008

Recently, with the growth of photovoltaic system, many researchers and companies have concerned about the multi-level inverter which has an efficiency of boosting voltage. In this paper a novel structure of multi-level converter for reducing ripple of output voltage is proposed. In the proposed converter Buck converters are connected in series to generate the output voltage and the ripple of output voltage can be reduced compared with the exiting Buck converter. Especially when outputting lower output voltage the number of acting switching elements is less and the result of ripple reducing is more obvious. This paper implements a multi-level switching function based on the FPGA.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.129-139
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• 2006

ARIA is a 128-bit block cipher, which became a Korean Standard in 2004. According to recent research this cipher is attacked by first order DPA attack In this paper, we explain a masking technique that is a countermeasure against first order DPA attack and apply it to the ARIA. And we implemented a masked ARIA for the 8 bit microprocessor based on AVR in software. By using this countermeasure, we verified that it is secure against first order DPA attack.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.4
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• pp.24-33
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• 1996

PLCs are vital components of modern automation systems, which have penetrated into almost every industry. Many industries have a demand for facilitation of PLC programming. In this study, a programning system for sequential control is developed on a personal computer. This programming system consists of two main parts, a GRAFCET editor and a GRAFCET compiler. The GRAFCET editor enables us to model an actual sequential process by a GRAFCET diagram. This GRAFCET editor is developed by the menu-driven method based on specific menus and graphic symbols. The GRAFCET compiler consists of two parts, a GRAFCET parser and a code generator. The possible errors in a drawn GRAFCET diagram are first checked by the GRAFCET parser which generates finally an intermediate code from a verified CRAFCET diagram. Then the intermediate code is converted into a control code of an actual sequential controller by the code generator. To show the usefulness of this programming system, this system is applied to a pneumatically controlled handling robot. For this robot, a Z-80 microprocessor is used as the actual sequential controller.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.115-121
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• 2023

RISC-V is an open-source instruction set architecture, and anyone can freely design and implement a RISC-V microprocessor. This paper designes and simulates the RISC-V architecture, synthesizing it in FPGA and verifying it using logic analyzer (ILA). RISC-V core is written in SystemVerilog, which has efficient design and high reusability, and can be used in various application fields. The RISC-V core is implemented as hardware by synthesizing it on the Ultra96-V2 FPGA board using Vivado, and the accuracy and operation of the design are verified through Integrated Logic Analyzer(ILA). As a result of the experiment, it is confirmed that the designed RISC-V core performs the expected operation, and these results can contribute to the design and verification of RISC-V based systems.

• Journal of Information Technology Services
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• v.8 no.2
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• pp.147-156
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• 2009

As the result of the rapid development of IT technology, an on-line diagnostic system using the field bus communication network coupled with a smart sensor module will be widely used at the nuclear power plant in the near future. The smart sensor system is very useful for the prompt understanding of abnormal state of the key equipments installed in the nuclear power plant. In this paper, it is assumed that a smart sensor system based on the fieldbus communication network for the surveillance and diagnostics of safety-critical equipments will be installed in the harsh-environment of the nuclear power plant. It means that the key components of fieldbus communication system including microprocessor, FPGA, and ASIC devices, are to be installed in the RPV (reactor pressure vessel) and the RCS (reactor coolant system) area, which is the area of a high dose-rate gamma irradiation fields. Gamma radiation constraints for the DBA (design basis accident) qualification of the RTD sensor installed in the harsh environment of nuclear power plant, are typically on the order of 4 kGy/h. In order to use a field bus communication network as an ad-hoc diagnostics sensor network in the vicinity of the RCS pump area of the nuclear power plant, the robust survivability of IT-based micro-electronic components in such intense gamma-radiation fields therefore should be verified. An intelligent CCD camera system, which are composed of advanced micro-electronics devices based on IT technology, have been gamma irradiated at the dose rate of about 4.2kGy/h during an hour UP to a total dose of 4kGy. The degradation performance of the gamma irradiated CCD camera system is explained.

• Journal of Internet Computing and Services
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• v.14 no.4
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• pp.85-90
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• 2013

Currently, the electric fire prediction system uses PIC(Peripheral Interface Controller) for controller microprocessor. PIC has a slower computing speed than DSP does, so its real-time computing ability is inadequate. So with the basic characteristics waveform during arc generation as the standard reference, the comparison to this reference is used to predict and alarm electric fire from arc. While such alarm can be detected and taken care of from a remote central server, that prediction error rate is high and remote control in mobile environment is not available. In this article, the arc detection of time domain and frequency domain and wavelet-based adaptation algorithm executing the adaptation algorithm in conversion domain were applied to develop an electric fire prediction system loaded with new real-time arc detection algorithm using DSP. Also, remote control was made available through iPhone environment-based app development which enabled remote monitoring for arc's electric signal and power quality, and its utility was verified.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.1-12
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• 1999

In this paper, we designed an embedded processor with 128Kbytes EPROM and 4Kbytes SRAM based on GMS30C2132 which RISC processor with DSP functions. And a new architecture of bus sharing to control the embedded memory and external memory unit i proposed aiming at one-cycle access between memories and CPU. For embedded 128Kbytes EPROM, we designed the new expansion interface for data size at data ordering with memory organization and the efficient interface for test. The embedded SRAM supports an extended stack area high speed DSP operation, instruction cache and variable data-length control which is accessed with 4K modulo addressing schemes. The proposed new architecture and circuits reduced the memory access cycle time from 40ns and improved operation speed 2-times for program benchmark test. The chip is occupied $108.68mm^2$ using $0.6{\mu}m$ CMOS technology.