• Journal of the Korean Society for Precision Engineering
• /
• v.1 no.2
• /
• pp.69-74
• /
• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.33 no.2
• /
• pp.62-69
• /
• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2900 "bit-slice" microprocessor chips and 0.5K ROMs of 36-bit microprogram memory. The system design is an instuction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolation speed of 250 K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software, and experimental results are presented.presented.

• ETRI Journal
• /
• v.26 no.6
• /
• pp.513-519
• /
• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• Proceedings of the KIEE Conference
• /
• 1989.07a
• /
• pp.134-137
• /
• 1989

A digital controller for a discrete-data control system can take many forms. For example, they can be passive RC networks, general purpose digital computers, special purpose of mini-computer, and delay lines. With the recent advent of the microprocessor, its use as a digital controller is evident. This work discusses the hardware and software development of a microprocessor-based digital controller for a discrete-data control system. A second-order, Type 1 system is implemented on an analog computer; a Intel 80-286 microprocessor is used to implemented the controller; and, output response are obtained for step, ramp, and parabolic inputs. The results demonstrate that the microprocessor has potential as a digital controller. Finally, a brief discussion on the results indicate possible areas of improvement of the controller and future investigation.

• Proceedings of the KIEE Conference
• /
• 1990.07a
• /
• pp.413-417
• /
• 1990

Various sampling methods are used for microprocessor-based measurement and analysis to nonsinusoidal waveforms caused by power electronic converters. The hamonic component generates the indicating errors at the measuring instruments. This can be solved by microprocessor-based measurement and hence the microprocessor-based measuring equipment and its algorithm are developed in this paper. As a result the suggested equipment has very good measuring performances.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.8
• /
• pp.109-115
• /
• 2005

This paper addresses the CAN based networked intelligent multi-motor control system using DSP2812 microprocessor. CAN built in DSP2812 microprocessor is used to control and monitor the multi-motor system with the inverter driving system CAN network implementation schemes and the algorithm for multi-motor control and monitoring is also developed. We configure the multi-motor control experimental system to verify the proposed algerian and the reliability of CAN networks system in the various operation of two induction motors. The experimental results show that CAN based networked intelligent multi-motor control system using DSP2812 microprocessor can carry out the real-time network based control in various speed range and the position control of induction motors.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• v.2B no.4
• /
• pp.207-213
• /
• 2002

The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.16 no.3
• /
• pp.19-27
• /
• 1979

Microprocessor based digital filter was designed rising focus number system in order to increase the multiplication speed of microprocessor program. Addition and subtraction program was treated using look up table. The sampling speed was improved up to 500 samples per seconds on the third-order low- Pass digital filters.

• Journal of Korean Society for Quality Management
• /
• v.28 no.1
• /
• pp.27-40
• /
• 2000

Technological forecasting for microprocessor market can provide timely insight into the prospects for significant technological changes in computer hardware as well as software. In this paper, we use bibliometrics to forecast R&D trend on microprocessor technology. Cumulative numbers of US Patents on several generations of microprocessor technology (pipeline, superpipeline, supersclar and VLIW) approved since 1980 are applied to fit diffusion models. Our study results provide both the maximum market potential and the maturity time for each generation of microprocessor technology. Such information is expected to make contribution on making better decisions with regard to strategic corporate planning, R&D management, product development and investment in new technology of microprocessor.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.408-411
• /
• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.