• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.466-476
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• 1986

This paper proposes a system that translates the machine independent intermediate micro-programming language(IML) into microcode, using the register allocation algorithm, the microinstruction format and the field information for the target machine emulation on a microprogrammable host machine. The IML, which is for PDP-8 emulation on a microprogrammable hypothsetical 16 bit host machine, is microcoded by the proposed system, and the validity of the algorithm in the proposed system is verified by executing a test program of the target machine on the emulator.