• Journal of Welding and Joining
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• v.29 no.1
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• pp.52-58
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• 2011

In this paper, the direct bonding process between FPCB and HPCB was studied. By using an ultrasonic horn which is mounted on the ultrasonic bonding machine, it is alternatively possible to bond the gold pads attached on the FPCB and HPCB at room temperature without an adhesive like ACA or NCA. The process condition for obtaining more bonding strength than 0.6 Kgf, which is commercially required, was carried out as 40 kHz of frequency, 0.6 MPa of bonding pressure and 2 second of bonding time. The peel off test was performed for evaluating bonding strength which results in more than 0.8 Kgf.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.11
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• pp.979-983
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• 2013

The three-dimensional measurement method of confocal systems is a spot scanning method which has a high resolution and good illumination efficiency. However, conventional confocal systems had a weak point in that it has to perform XY axis scanning to achieve FOV (Field of View) vision through spot scanning. There are some methods to improve this problem involving the use of a galvano mirror [1], pin-hole array, etc. Therefore, in this paper we propose a method to improve a parallel mode confocal system using a micro-lens and pin-hole array in a dual microscope configuration. We made an area scan possible by using a combination MLA (Micro Lens Array) and pin-hole array, and used an objective lens to improve the light transmittance and signal-to-noise ratio. Additionally, we made it possible to change the objective lens so that it is possible to select a lens considering the reflection characteristic of the measuring object and proper magnification. We did an experiment using 5X, 2.3X objective lens, and did a calibration of height using a VLSI calibration target.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.577-580
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• 2005

Surface quality of a micro-processed sample with laser has been investigated by using of scanning confocal microscope(SCM) and atomic force microscope(AFM). Samples are bump electrodes and ITO glass of LCD module used in a mobile phone and a wafer surface scribed by UV laser. A image of $140\times120{\mu}m^2$ is obtained within 1 second by SCM because scan speed of a x-axis and y-axis are 1kHz and 1Hz, respectively. AFM is able to measure correctly hight and width of ITO and scribing depth and width of a wafer with a resolution less than 300 . However, the scan speed is slow and it is difficult to distinguish a surface composed of different nm kinds of materials. Results show that SCM is preferable to obtain a image of a sample composed of different kinds of material than AFM because the intensity of a reflected light from surface is different from each material.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.235-237
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• 2007

In this paper, fabrication of Sn-3.0Ag-0.5Cu solder bumping having accurate composition and behavior of intermetallic compounds(IMCs) growth at interface between Sn-Ag-Cu bumps and Cu substrate were studied. The ternary alloy of the Sn-3.0Ag-0.5Cu solder was made by two binary(Sn-Cu, Sn-Ag) electroplating on Cu pad. For the manufacturing of the micro-bumps, photo-lithography and reflow process were carried out. After reflow process, the micro-bumps were aged at $150^{\circ}C$ during 1 hr to 500 hrs to observe behavior of IMCs growth at interface. As a different of Cu contents(0.5 or 2wt%) at Sn-Cu layer, behavior of IMCs was estimated. The interface were observed by FE-SEM and TEM for estimating of their each IMCs volume ratio and crystallographic-structure, respectively. From the results, it was found that the thickness of $Cu_3Sn$ layer formed at Sn-2.0Cu was thinner than the thickness of that layer be formed Sn-0.5Cu. After aging treatment $Cu_3Sn$ was formed at Sn-0.5Cu layer far thinner.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.53-57
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• 2011

In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• Proceedings of the Korean Reliability Society Conference
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• 2000.04a
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• pp.97-103
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• 2000

전자 산업의 발달에 따라 전자 패키지에서 소자의 소형화 및 고집적화가 가속화되고 그로 인해 interconnection 부분의 신뢰성 평가의 중요성이 나날이 증가되고 있다. 특히 이러한 interconnection 부분 중 솔더 접합부는 사용중 솔더와 UBM(Under Bump Metallurgy) 층 사이에 금속간화합물이 생성되어 접합 강도가 저하되는 것이 큰 문제로 지적되고 있다. 본 연구에서는 공정 Sn-Ag 솔더 접합부에 대해 열시효 시간에 따라 접합 강도를 측정하고 파괴 기구 및 파괴 경로의 분석을 통해 접합 강도 변화와의 연관성을 도출하고자 하였다. 그 결과 열시효 초기에는 미세 조직의 조대화 및 불균일 조대 성장이 가속화되면서 응력 및 변형 집중으로 인해 솔더 내부에서 연성 파괴가 일어나 급격한 접합 강도의 저하가 발생하였으나 금속간 화합물이 생성, 성장함에 따라 금속간 화합물 내부에서의 취성 파괴가 나타나면서 접합 강도 저하가 포화되는 경향을 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional R layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at 330$^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.9-14
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• 2007

In this study, the thermal reliability on flip chip package with non-conductive pastes (NCPs) was evaluated under accelerated conditions. As the number of thermal shock cycle and the dwell time of temperature and humidity condition increased, the electrical resistance of the flip chip package with NCPs increased. These phenomenon was occurred by the crack between Au bump and Au bump and the delamination between chip or substrate and NCPs during the thermal shock and temperature and humidity tests. And the variation of electrical resistance during temperature and humidity test was larger than that during thermal shock test. Therefore it was identified that the flip chip package with NCPs was sensitive to environment with moisture.