• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.348-352
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• 2007

In submicron processes, the feature size of ULSI devices is critical, and it is necessary both to reduce the RC time delay for device speed performance and to enable higher current densities without electromigration. In case of contacts between semiconductor and metal in semiconductor devices, it may be very unstable during the thermal annealing process. To prevent these problems, we deposited tungsten carbon nitride (W-C-N) ternary compound thin film as a diffusion barrier for preventing the interdiffusion between metal and semiconductor. The thickness of W-C-N thin film is $1,000{\AA}$ and the process pressure is 7mTorr during the deposition of thin film. In this work we studied the interface effects W-C-N diffusion barrier using the XRD and 4-point probe.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.31-36
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• 2000

We developed embedded inductors in MCM-D substrate for RF applications. The increasing demand for high density packaging was the driving forces to the development of MCM-D technology. Most of these development efforts have been focused on high performance digital circuits. However, recently there is a great need fur mixed mode circuits with a combination of digital, analog and microwave devices. Mixed mode modules often have a large number of passive components that are connected to a small number of active devices. Integration of passive components into the high density MCM substrate becomes desirable to further reduce cost, size, and weight of electronic systems while improving their performance and reliability. The proposed MCM-D substrate was based on Cu/photosensitive BCB multilayer and Ti/Cu is used to form the interconnect layer. Seed metal was formed with 1000 $\AA$ Ti/3000 $\AA$ Cu by sputtering method and main metal was formed with 3 $\mu\textrm{m}$ Cu by electrical plating method. The multi-turn sprial inductors were designed in coplanar fashion. This paper describe the manufacturing process of integrated inductors in MCM-D substrate and the results of electrical performance test.

• Korean Chemical Engineering Research
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• v.48 no.2
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• pp.172-177
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• 2010

This study reports the high-temperature oxidation kinetics, ASR(area specific resistance), and interfacial microstructure of metallic interconnects coated with conductive oxides in oxidation atmosphere at $800^{\circ}C$, The conductive material LSC($La_{0.8}Sr_{0.2}CoO_3$, prepared by Solid State Reaction) was coated on the Crofer22APU. The contact behavior of coating layer/metal substrate was increased by sandblast. The electrical conductivity of the LSC coated Crpfer22APU was measured by a DC two probe four wire method for 4000hr, in air at $800^{\circ}C$. Microstructure and composition of the coated layer interface were investigated by SEM/EDS. These results show that a coated LSC layer prevents the formation and growth of oxide scale such as $Cr_2O_3$ and enhances the long-term stability and electrical performance of metallic interconnects for SOFCs.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.338-338
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• 2013

Monolithic three-dimensional integrated circuits (3D-ICs) 구현 시 bonding 과정에서 발생되는 aluminum (Al) 이나 copper (Cu) 등의 interconnect metal의 확산, 열적 스트레스, 결함의 발생, 도펀트 재분포와 같은 문제들을 피하기 위해서는 저온 공정이 필수적이다. 지금까지는 polymer 기반의 bonding이나 Cu/Cu와 같은 metal 기반의 bonding 등과 같은 저온 bonding 방법이 연구되어 왔다. 그러나 이와 같은 bonding 공정들은 공정 시 void와 같은 문제가 발생하거나 공정을 위한 특수한 장비가 필수적이다. 반면, 두 물질의 합금을 이용해 녹는점을 낮추는 eutectic bonding 공정은 저온에서 공정이 가능할 뿐만 아니라 void의 발생 없이 강한 bonding 강도를 얻을 수 있다. Aluminum-germanium (Al-Ge) 및 aluminum-indium (Al-In) 등의 조합이 eutectic bonding에 이용되어 각각 $424^{\circ}C$ 및 $454^{\circ}C$의 저온 공정을 성취하였으나 여전히 $400^{\circ}C$이상의 eutectic 온도로 인해 3D-ICs의 구현 시에는 적용이 불가능하다. 이러한 metal 조합들에 비해 indium (In)과 tin (Sn)은 각각 $156^{\circ}C$ 및 $232^{\circ}C$로 굉장히 낮은 녹는점을 가지고 있기 때문에 In-Sn 조합은 약 $120^{\circ}C$ 정도의 상당히 낮은eutectic 온도를 갖는다. 따라서 본 연구팀은 In-Sn 조합을 이용하여 $200^{\circ}C$ 이하에서monolithic 3D-IC 구현 시 사용될 eutectic bonding 공정을 개발하였다. 100 nm SiO2가 증착된 Si wafer 위에 50 nm Ti 및 410 nm In을 증착하고, 다른Si wafer 위에 50 nm Ti 및 500 nm Sn을 증착하였다. Ti는 adhesion 향상 및 diffusion barrier 역할을 위해 증착되었다. In과 Sn의 두께는 binary phase diagram을 통해 In-Sn의 eutectic 온도인 $120^{\circ}C$ 지점의 조성 비율인 48 at% Sn과 52 at% In에 해당되는 410 nm (In) 그리고 500 nm (Sn)로 결정되었다. Bonding은 Tbon-100 장비를 이용하여 $140^{\circ}C$, $170^{\circ}C$ 그리고 $200^{\circ}C$에서 2,000 N의 압력으로 진행되었으며 각각의 샘플들은 scanning electron microscope (SEM)을 통해 확인된 후, 접합 강도 테스트를 진행하였다. 추가로 bonding 층의 In 및 Sn 분포를 확인하기 위하여 Si wafer 위에 Ti/In/Sn/Ti를 차례로 증착시킨 뒤 bonding 조건과 같은 온도에서 열처리하고secondary ion mass spectrometry (SIMS) profile 분석을 시행하였다. 결론적으로 본 연구를 통하여 충분히 높은 접합 강도를 갖는 In-Sn eutectic bonding 공정을 $140^{\circ}C$의 낮은 공정온도에서 성공적으로 개발하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.377-377
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• 2012

Microprocessor technology now relies on copper for most of its electrical interconnections. Because of the high diffusivity of copper, Atomic layer deposition (ALD) $TaN_x$ is used as a diffusion barrier to prevent copper diffusion into the Si or $SiO_2$. Another problem with copper is that it has weak adhesion to most materials. Strong adhesion to copper is an essential characteristic for the new barrier layer because copper films prepared by electroplating peel off easily in the damascene process. Thus adhesion-enhancing layer of cobalt is placed between the $TaN_x$ and the copper. Because, cobalt has strong adhesion to the copper layer and possible seedless electro-plating of copper. Until now, metal film has generally been deposited by physical vapor deposition. However, one draw-back of this method is poor step coverage in applications of ultralarge-scale integration metallization technology. Metal organic chemical vapor deposition (MOCVD) is a good approach to address this problem. In addition, the MOCVD method has several advantages, such as conformal coverage, uniform deposition over large substrate areas and less substrate damage. For this reasons, cobalt films have been studied using MOCVD and various metal-organic precursors. In this study, we used $C_{12}H_{10}O_6(Co)_2$ (dicobalt hexacarbonyl tert-butylacetylene, CCTBA) as a cobalt precursor because of its high vapor pressure and volatility, a liquid state and its excellent thermal stability under normal conditions. Furthermore, the cobalt film was also deposited at various $H_2/NH_3$ gas ratio(1, 1:1,2,6,8) producing pure cobalt thin films with excellent conformality. Compared to MOCVD cobalt using $H_2$ gas as a reactant, the cobalt thin film deposited by MOCVD using $H_2$ with $NH_3$ showed a low roughness, a low resistivity, and a low carbon impurity. It was found that Co/$TaN_x$ film can achieve a low resistivity of $90{\mu}{\Omega}-cm$, a low root-mean-square roughness of 0.97 nm at a growth temperature of $150^{\circ}C$ and a low carbon impurity of 4~6% carbon concentration.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.518-522
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• 2008

The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.80.1-80.1
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• 2010

A strontium titanate ($SrTiO_3$)-based material with a perovskite structure is considered to be one of the promising alternatives to $LaCrO_3$-based materials since $SrTiO_3$ perovskite shows a high chemical stability under both oxidizing and reducing atmospheres at high temperatures. $SrTiO_3$ materials exhibit an n-type semiconducting behavior when it is donor-doped and/or exposed to a reducing atmosphere. In this work, $Sr_{1-x}La_xTi_{1-y}M_yO_3$ materials doped with $La^{3+}$ in A-sites and aliovalent transition metal ions ($M^{n+}$) in B-sites were synthesized by the modified Pechini method. The X-ray diffraction analysis indicated that the materials synthesized by the Pechini process exhibited a single curbic perovskite-type structure without any impurity phases, and are tolerant, to some extent, to cation doping. The sintering behaviors of $Sr_{1-x}La_xTi_{1-y}M_yO_3$ in $H_2/N_2$ and air were characterized by dilatometry and microstructural observations. The electrical conduction mechanism and the dopant effect are discussed based on the defect structures and the electrical conductivities measured at various oxygen partial pressures and temperatures.