• Title/Summary/Keyword: Mesh cell size control

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A NEW CELL SIZING METHOD FOR AUTOMATIC UNSTRUCTURED GRID GENERATION USING CAD SURFACE DATA (CAD 형상 데이터를 이용한 비정렬 격자 자동 생성을 위한 격자셀 크기 지정 기법)

  • Lee, B.J.;Kim, B.S.
    • 한국전산유체공학회:학술대회논문집
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    • 2007.10a
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    • pp.120-125
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    • 2007
  • In this paper a new cell sizing method is proposed. The new method calculates cell size at a point using given size control elements directly without the aid of background grid as other cell sizing algorithms do. The calculation method and related definitions are described in detail, and typical cell sizing results are given.

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Study on Supersonic Jet Noise Reduction Using a Mesh Screen (메쉬 스크린을 이용한 초음속 제트소음 저감법에 관한 실험적 연구)

  • Kweon, Yong-Hun;Lim, Chae-Min;Kim, Heuy-Dong
    • Proceedings of the Korean Society of Propulsion Engineers Conference
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    • 2006.11a
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    • pp.377-381
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    • 2006
  • This paper describes experimental work to control supersonic jet noise using a mesh screen that is placed at the nozzle exit plane. The mesh screen is a wire-gauze screen that is made of long stainless wires with a very small diameter. The nozzle pressure ratio is varied to obtain the supersonic jets which are operated in a wide range of over-expanded to moderately under-expanded jets. In order to perturb mainly the initial jet shear layer, the hole is perforated in the central part of the mesh screen. The hole size is varied to investigate the noise control effectiveness of the mesh screen. A schlieren optical system is used to visualize the flow fields of supersonic jet with and without the mesh screen device. Acoustic measurement is performed to obtain the OASPL and noise spectra. The results obtained show that the present mesh screen device leads to a substantial suppression of jet screech tones. The hole size is an important factor in reducing the supersonic jet noise. For over-expanded jets, the noise control effectiveness of the mesh screen appears more significant, compared to correctly and under-expanded jets

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High fidelity transient solver in STREAM based on multigroup coarse-mesh finite difference method

  • Anisur Rahman;Hyun Chul Lee;Deokjung Lee
    • Nuclear Engineering and Technology
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    • v.55 no.9
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    • pp.3301-3312
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    • 2023
  • This study incorporates a high-fidelity transient analysis solver based on multigroup CMFD in the MOC code STREAM. Transport modeling with heterogeneous geometries of the reactor core increases computational cost in terms of memory and time, whereas the multigroup CMFD reduces the computational cost. The reactor condition does not change at every time step, which is a vital point for the utilization of CMFD. CMFD correction factors are updated from the transport solution whenever the reactor core condition changes, and the simulation continues until the end. The transport solution is adjusted once CMFD achieves the solution. The flux-weighted method is used for rod decusping to update the partially inserted control rod cell material, which maintains the solution's stability. A smaller time-step size is needed to obtain an accurate solution, which increases the computational cost. The adaptive step-size control algorithm is robust for controlling the time step size. This algorithm is based on local errors and has the potential capability to accept or reject the solution. Several numerical problems are selected to analyze the performance and numerical accuracy of parallel computing, rod decusping, and adaptive time step control. Lastly, a typical pressurized LWR was chosen to study the rod-ejection accident.

Development and verification of pin-by-pin homogenized simplified transport solver Tortin for PWR core analysis

  • Mala, Petra;Pautz, Andreas
    • Nuclear Engineering and Technology
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    • v.52 no.11
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    • pp.2431-2441
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    • 2020
  • Currently, the pin-by-pin homogenized solvers are a very active research field as they can, unlike the nodal codes, directly predict the local power, while requiring significantly less computational resources than the heterogeneous transport codes. This paper presents a recently developed pin-by-pin diffusion/SP3 solver Tortin, its spatial discretization method and the reflector treatment. Regarding the spatial discretization, it was observed that the finite difference method applied on pin-cell size mesh does not properly capture the big flux change between MOX and uranium fuel, while the nodal expansion method is more accurate but too slow. If the finite difference method is used with a finer mesh in the outer two pin rows of the fuel assembly, it increases the required computation time by only 50%, but decreases the pin power errors below 1% with respect to lattice code reference solutions. The paper further describes the coupling of Tortin with a microscopic depletion solver. Several verification tests show that the SP3 pin-by-pin solver can reproduce the heterogeneous transport solvers results with very good accuracy, even for fuel cycle depletion of very heterogeneous core employing MOX fuel or inserted control rods, while being two orders of magnitude faster.

Development of a CAD-based Utility for Topological Identification and Rasterized Mapping from Polygonal Vector Data (CAD 수단을 이용한 벡터형 공간자료의 위상 검출과 격자도면화를 위한 유틸리티 개발)

  • 조동범;임재현
    • Journal of the Korean Institute of Landscape Architecture
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    • v.27 no.4
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    • pp.137-142
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    • 1999
  • The purpose of this study is to develope a CAD-based tool for rasterization of polygonal vector map in AutoCAD. To identity the layer property of polygonal entity with user-defined coordinates as topology, algorithm in processing entity data of selection set that intersected with scan line was used, and the layers were extracted sequentially by sorted intersecting points in data-list. In addition to the functions for querying and modifying topology, two options for mapping were set up to construct plan projection type and to change meshes' properties in existing DTM data. In case of plan projection type, user-defined cell size of 3DFACE mesh is available for more detailed edge, and topological draping on landform can be executed in case of referring DTM data as an AutoCAD's drawing. The concept of algorithm was simple and clear, but some unexpectable errors were found in detecting intersected coordinates that were AutoCAD's error, not the utility's. Also, the routines to check these errors were included in algorithmic processing. Developed utility named MESHMAP was written in entity data control functions of AutoLISP language and dialog control language(DCL) for the purpose of user-oriented interactive usage. MESHMAP was proved to be more effective in data handling and time comparing with GRIDMAP module in LANDCADD which has similar function.

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The effects of light colour on female rabbit reproductive performance and the expression of key genes in follicular development

  • Xiaoqing, Pan;Xinglong, Wang;Le, Shao;Jie, Yang;Feng, Qin;Jian, Li;Xia, Zhang;Pin, Zhai
    • Journal of Animal Science and Technology
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    • v.64 no.3
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    • pp.432-442
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    • 2022
  • The purpose of this study was to analyse the effects of light colour on rabbit reproductive performance and the expression of key follicular development genes. Rabbits (n = 1,068, 5 months old, 3.6-4.4 kg live body weight) were divided randomly into four groups, housed individually in wire mesh cages and exposed to red, green, blue, and white light-emitting diode (LED) light (control). The lighting schedule was 16 L : 8 D-15 d / 150 lx / 6:00 am-22:00 pm (3 d preartificial insemination to 12 d postartificial insemination). Red light and white light affected the conception rate and kindling rate and increased the total litter size at birth (p < 0.05). The effects of red light on litter size at weaning, litter weight at weaning, and individual weight at weaning increased compared with the green and blue groups. The effects of red light on live litter size at birth were increased compared with those in the blue group (p < 0.05). Compared to white light, green and blue light reduced the number of secondary follicles (p < 0.05). Compared to red light, green and blue light reduced the number of tertiary follicles (p < 0.05). Compared with white light, red LED light resulted in greater ovarian follicle stimulating hormone receptor and luteinizing hormone receptor mRNA expression (p < 0.05). Compared with green and blue LED light, red LED light resulted in greater B-cell lymphom-2 mRNA expression (p < 0.05). Compared with green LED light, red LED light inhibited FOXO1 mRNA expression in rabbit ovaries (p < 0.05). Red light can affect the reproductive performance of female rabbits and the expression of key genes for follicular development.

A VLSI Architecture of Systolic Array for FET Computation (고속 퓨리어 변환 연산용 VLSI 시스토릭 어레이 아키텍춰)

  • 신경욱;최병윤;이문기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.9
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    • pp.1115-1124
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    • 1988
  • A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

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