• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.647-650
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• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.89-95
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• 2008

In this paper, we designed a low power face detection hardware and analysed its power consumption. The face detection hardware was fabricated using Samsung 0.18um CMOS technology and it can detect multiple face locations from a 2-D image. The hardware is composed of 6 functional modules and 11 internal memories. We introduced two operating modes(SLEEP and ACTIVE) to save power and a clock gating technique was used at two different levels: modules and registers. In additional, we divided an internal memory into several pieces to reduce the energy consumed when accessing memories, and fully utilized low power design option provided in Synopsis Design Compiler. As a result, we could obtain 68% power reduction in ACTIVE mode compared to the original design in which none of the above low power techniques were used.

• Investigative Magnetic Resonance Imaging
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• v.21 no.4
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• pp.199-209
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• 2017

Purpose: Caffeine is the most widely consumed psychostimulant. It is often adopted as a tool to modulate brain activations in fMRI studies. However, its pharmaceutical effect on task-induced deactivation has not been fully examined in fMRI. Therefore, the purpose of this study was to examine the effect of caffeine on both activation and deactivation under sustained attention. Materials and Methods: Task fMRI was acquired from 26 caffeine naive healthy volunteers before and after taking caffeine pill (200 mg). Results: Statistical analysis showed an increase in cognition-load dependent task activation but a decrease in load dependent de-activation after caffeine ingestion. Increase of attention and memory task activation and its load-dependence suggest a beneficial effect of caffeine on the brain even though it has no overt behavior improvement. The reduction of deactivation by caffeine and its load-dependence indicate reduced facilitation from task-negative networks. Conclusion: Caffeine affects brain activity in a load-dependent manner accompanied by a disassociation between task-positive network and task-negative network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.41-52
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• 2011

It is important to reduce computational complexity of de-blocking filter for real-time implementation, because it accounts for a great part of total computational complexity of the decoder. Because there are a lot of conditional branches and memory accesses in a decoding loop, it is not easy to speed up the de-blocking filter. Therefore, this paper presents a new algorithm of de-blocking filter minimizing conditional branches and memory accesses. The proposed structure of de-blocking filter enables filter operation to parallelize by software pipelining. The proposed optimization method was implemented on a TMS320DM6467 EVM board and we achieved approximately 46% cycle reduction, compared with that of FFmpeg.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.59-62
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• 1996

Plasma displays (PDP) as a large area wall-hanging display device are rabidly developed with flat CRT, TPT LCD and etc. Especially, AC Plasma Display Panels(AC PDPs) have the inherent memory function which is effective for large area displays. The memory function in AC PDPs is caused by the accumulation of the electrical charge on the protecting layer formed on the dielectric layer. This MgO protective layer prevents the dielectric layer from sputtering by ion in discharge plasma and also has the additional important roll in lowering the firing voltage due to the large secondary electron emission coefficient). Until now, the MgO Protective layer is mainly formed by E-Beam evaporation. With increasing the panel size, this process is difficult to attain cost reduction, and are not suitable for large quantity of production. To the contrary, the methode of shuttering are easy to apply on mass production and to enlarge the size of the panel and shows the superior adhesion and uniformity of thin film. In this study, we have prepared MgO protective layer on AC PDP Cell by reactive magnetron sputtering and studied the effect of MgO layer on the surface discharge characteristics of ac PDP.

• Journal of KIISE:Software and Applications
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• v.32 no.3
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• pp.227-235
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• 2005

In the embedded system domain, both memory requirement and energy consumption are great concerns. To save memory and energy, the 32 bit ARM processor supports the 16 bit Thumb instruction set. For a given program, the Thumb code is typically smaller than the ARM code. However, the limitations of the Thumb instruction set can often lead to generation of poorer quality code. To generate codes with smaller size but a little slower execution speed, Krishnaswarmy suggests a profiling guided selection algorithm at module level for generating mixed ARM and Thumb codes for application programs. The resulting codes of the algorithm give significant code size reductions with a little loss in performance. When the instruction set is selected at module level, some functions, which should be compiled in Thumb mode to reduce code size, are compiled to ARM code. It means we have additional code size reduction chance. In this paper, we propose a profile guided selection algorithm at function level for generating mixed ARM and Thumb codes for application programs so that the resulting codes give additional code size reductions without loss in performance compared to the module level algorithm. We can reduce 2.7％ code size additionally with no performance penalty

• Journal of the Korea Convergence Society
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• v.4 no.1
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• pp.21-26
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• 2013

Due to a lack of research regarding disruptive technologies in domestic research, the purpose of this study is to aid in the understanding of disruptive technologies through empirical analysis of cases selected in the computer data storage industry. Analysis results have shown that SSDs, which threaten the existence of HDDs, adhere to the conditions of being a disruptive technology as first presented by Christensen(1992). SSDs are not only technologically superior to HDDs but can be mass produced due to its applicability in a vast array of product categories made possible by their miniaturization, weight reduction, and safety. This diversity of applicable fields makes it possible for mass production leading to further decrease in the unit price ultimately continuing the diffusion of this technology. By presenting empirical cases to aid in the understanding of disruptive technology, it is determined that the findings of this study contribute greatly to both academia and the business world.