• Bulletin of the Korean Mathematical Society
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• v.55 no.4
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• pp.1303-1315
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• 2018

For principal component analysis (PCA) to efficiently analyze large scale matrices, it is crucial to find a few singular vectors in cheaper computational cost and under lower memory requirement. To compute those in a fast and robust way, we propose a new stochastic method. Especially, we adopt the stochastic variance reduced gradient (SVRG) method [11] to avoid asymptotically slow convergence in stochastic gradient descent methods. For that purpose, we reformulate the PCA problem as a unconstrained optimization problem using a quadratic penalty. In general, increasing the penalty parameter to infinity is needed for the equivalence of the two problems. However, in this case, exact penalization is guaranteed by applying the analysis in [24]. We establish the convergence rate of the proposed method to a stationary point and numerical experiments illustrate the validity and efficiency of the proposed method.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1595_1596
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• 2009

In this study reduction effects of magnetic field were analyzed using multi-conductor method in analysis of shield. The method can be effective in the analysis because of reducing the amount of allocated memory and computing time. And also the method can be applicable to analysis of the induced current distributions and skin effect in shield. The results of the analysis are presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.1023-1029
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• 2011

In the industrial vision systems, image correction has great influence on the overall performance of measurement or inspection. The overall area of distorted image is usually splitted into small control areas, and each area is corrected by its control points. The performance of correction methods using control points can be improved by reduction of control areas because the computational time and memory highly depend on the number of control areas. We develop a merging algorithm that reduces control areas and preserves the correction accuracy. The algorithm merges the splitted control areas by use of quad tree method. Experimental results are presented to verify the usefulness of the proposed method.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.3
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• pp.1182-1194
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• 2016

The single image dehazing algorithm in existence can satisfy the demand only for improving either the effectiveness or efficiency. In order to solve the problem, a novel variational framework for single image dehazing based on restoration is proposed. Firstly, the initial atmospheric scattering model is transformed to meet the kimmel's Retinex variational model. Then, the green light component of image is considered as an input of the variational framework, which is generated by the sensitivity of green wavelength. Finally, the atmospheric transmission map is achieved by multi-resolution pyramid reduction to improve the visual effect of the results. Experimental results demonstrate that the proposed method can remove haze effectively with less memory consumption.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Journal of Mechanical Science and Technology
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• v.15 no.11
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• pp.1572-1579
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• 2001

We investigate the possibility of application of the Goore Scheme to turbulence control for drag reduction. In Part I, we examine the performance of the original Goore Scheme by applying it to a si mple one-dimensional problem. For the application of the scheme to turbulence control, we extend the scheme's capability so that it can treat multi-dimensional problems and examine its validity theoretically. The convergence of the extended scheme with a dynamic memory is faster by an order of magnitude than the original scheme. In Part II, we apply the proposed scheme to reduce drag for turbulent channel flows through direct numerical simulation.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• Journal of Korea Society of Digital Industry and Information Management
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• v.17 no.2
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• pp.1-11
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• 2021

Salt and pepper is a type of impulse noise. It may appear due to an error in the image transmission process and image storage memory. This noise changes the pixel value at any position in the image to 0 (in case of pepper noise) or 255 (in case of salt noise). In this paper, we present an algorithm for SAP noise reduction. The proposed method consists of three steps. In the first step, the location of the SAP noise is detected, and in the second step, the pixel value of the detected location is restored using a weighted average of the surrounding pixel values. In the last step, a reliability matrix around the reconstructed pixels is constructed, and additional correction is performed with a weighted average using this. As a result of the experiment, the proposed method appears to have similar or higher objective and subjective image quality than previous methods for almost all SAP noise ratios.

• Journal of Korea Multimedia Society
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• v.25 no.5
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• pp.676-684
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• 2022

As realistic media are widespread in various image processing areas, image or video compression is one of the key technologies to enable real-time applications with limited network bandwidth. Generally, image or video compression cause the unnecessary compression artifacts, such as blocking artifacts and ringing effects. In this study, we propose a Deep Residual Channel-attention Network, so called DRCAN, which consists of an input layer, a feature extractor and an output layer. Experimental results showed that the proposed DRCAN can reduced the total memory size and the inference time by as low as 47% and 59%, respectively. In addition, DRCAN can achieve a better peak signal-to-noise ratio and structural similarity index measure for compressed images compared to the previous methods.