• Smart Structures and Systems
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• v.24 no.3
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• pp.361-377
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• 2019

The stiffness of shape memory alloy (SMA) spring while in actuation is represented by an empirical model that is derived from the logistic differential equation. This model correlates the stiffness to the alloy temperature and the functionality of SMA spring as active variable stiffness actuator (VSA) is analyzed based on factors that are the input conditions (activation current, duty cycle and excitation frequency) and operating conditions (pre-stress and mechanical connection). The model parameters are estimated by adopting the nonlinear least square method, henceforth, the model is validated experimentally. The average correlation factor of 0.95 between the model response and experimental results validates the proposed model. In furtherance, the justification is augmented from the comparison with existing stiffness models (logistic curve model and polynomial model). The important distinction from several observations regarding the comparison of the model prediction with the experimental states that it is more superior, flexible and adaptable than the existing. The nature of stiffness variation in the SMA spring is assessed also from the Dynamic Mechanical Thermal Analysis (DMTA), which as well proves the proposal. This model advances the ability to use SMA integrated mechanism for enhanced variable stiffness actuation. The investigation proves that the stiffness of SMA spring may be altered under controlled conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1238-1244
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• 1999

In this paper, a new design of a triple-erroe-correcting (TEC) Reed-Solomon decoder is presented based on direct decoding method which is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 GF(2m) multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders needs 24 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of implementation. Futhermore, the proposed TEC Reed-Solomon decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4C
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• pp.191-196
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• 2011

In this paper, we propose a design method of Reed-Solomon (23, 17) decoder for UWB using direct decoding method. The direct decoding algorithm is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 $GF(2^m)$ multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders need about 20 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• Journal of Positioning, Navigation, and Timing
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• v.8 no.4
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• pp.209-214
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• 2019

Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Journal of the Korean Operations Research and Management Science Society
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• v.6 no.1
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• pp.65-70
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• 1981

L.G. Khachiyan's algorithm for solving a system of strict (or open) linear inequalities with integral coefficients is described. This algorithm is based on the construction of a sequence of ellipsoids in R$^n$ of decreasing n-dimensional volume and contain-ing feasible region. The running time of the algorithm is polynomial in the number of bits of computer core memory required to store the coefficients. It can be applied to solve linear programming problems in polynomially bounded time by the duality theorem of the linear programming problem. But it is difficult to use in solving practical problems. Because it requires the computation of a square roots, besides other arithmatic operations, it is impossible to do these computations exactly with absolute precision.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Smart Structures and Systems
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• v.13 no.3
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• pp.353-374
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• 2014

Recent studies were dedicated to the realization of measurements on stay-cable samples of different geometry and static conditions as available at several facilities. The elaboration of the acquired data showed a a satisfactory efficacy of the dampers made of NiTi wires in smoothing the cable oscillations. A further attempt to investigate the applicability of the achieved results beyond the specific case-studies represented by the tested cable-stayed samples is herein pursued. Comparative studies are carried out by varying the diameter of the NiTi wire so that similar measurements can be taken also from laboratory steel cables of reduced size. Details of the preparation of the Ni-Ti wires are discussed with particular attention being paid to the suppression of the creep phenomenon. The resulting shape of the hysteretic cycle differs according to the wire diameter, which affects the order of the fitting polynomial to be used when trying to retrieve the experimental results by numerical analyses. For a NiTi wire of given diameter, an estimate of the amount of dissipated energy per cycle is given at low levels of maximum strain, which correspond to a fatigue fracture life of the order of millions of cycles. The dissipative capability is affected by both the temperature and the cycling frequency at which the tests are performed. Such effects are quantified and an ageing process is proposed in order to extend the working temperature range of the damper to cold weathers typical of the winter season in Northern Europe and Canada. A procedure for the simulation of the shape memory alloy behavior in lengthy cables by finite element analysis is eventually outlined.

• Aerospace Engineering and Technology
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• v.8 no.2
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• pp.61-67
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• 2009

This paper proposes an on-board orbit data generation algorithm for geostationary satellites. The concept of the proposed algorithm is as follows. From the ground, the position and velocity deviations with respect to the assumed reference orbit are computed for 48 hours of time duration in 30 minutes interval, and the generated data are up-loaded to the satellite to be stored. From the table, three nearest data sets are selected to compute position and velocity deviation for asked epoch time by applying $2^{nd}$ order polynomial interpolation. The computed position and velocity deviation data are added to reference orbit to recover absolute orbit information. Here, the reference orbit is selected to be ideal geostationary orbit with a zero inclination and zero eccentricity. Thanks to very low computational burden, this algorithm allows us to generate orbit data at 1Hz or even higher. In order to support 48 hours autonomy, maximum 3K byte memory is required as orbit data storage. It is estimated that this additional memory requirement is acceptable for geostationary satellite application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.403-413
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• 2009

We compare three predistortion methods to prevent signal distortion and spectral re-growth due to the high PAPR (peak-to-average ratio) of OFDM signal and the non-linearity of high-power amplifiers. The three predistortion methods are pth order inverse, indirect learning architecture and look up table. The pth order inverse and indirect learning architecture methods requires less memory and has a fast convergence because these methods use a polynomial model that has a small number of coefficients. Nevertheless the convergence is fast due to the small number of coefficients and the simple computation that excludes manipulation of complex numbers by separate compensation for the magnitude and phase. The look up table method is easy to implement due to simple computation but has the disadvantage that large memory is required. Computer simulation result reveals that indirect learning architecture shows the best performance though the gain is less than 1 dB at $BER\;=\;10^{-4}$ for 64-QAM. The three predistorters are adaptive to the amplifier aging and environmental changes, and can be selected to the requirements for implementation.