• Journal of Information Processing Systems
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• v.13 no.3
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• pp.435-447
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• 2017

Associative and bidirectional associative memories are examples of associative structures studied intensively in the literature. The underlying idea is to realize associative mapping so that the recall processes (one-directional and bidirectional ones) are realized with minimal recall errors. Associative and fuzzy associative memories have been studied in numerous areas yielding efficient applications for image recall and enhancements and fuzzy controllers, which can be regarded as one-directional associative memories. In this study, we revisit and augment the concept of associative memories by offering some new design insights where the corresponding mappings are realized on the basis of a related collection of landmarks (prototypes) over which an associative mapping becomes spanned. In light of the bidirectional character of mappings, we have developed an augmentation of the existing fuzzy clustering (fuzzy c-means, FCM) in the form of a so-called collaborative fuzzy clustering. Here, an interaction in the formation of prototypes is optimized so that the bidirectional recall errors can be minimized. Furthermore, we generalized the mapping into its granular version in which numeric prototypes that are formed through the clustering process are made granular so that the quality of the recall can be quantified. We propose several scenarios in which the allocation of information granularity is aimed at the optimization of the characteristics of recalled results (information granules) that are quantified in terms of coverage and specificity. We also introduce various architectural augmentations of the associative structures.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.102-105
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• 2005

A Effective wall following plays important role for the mapping behaviors which determine the entire memory size and the shape of map before building a map. In case of wall following, attacking those cause by curved wall or obstacles brings a bad stuff that makes ripples on the moving trajectory. These types of ripples come to an end with problems that increase the load of calculation and sensing errors. In this paper, a new sensing method and its corresponding controller are suggested for problems. It minimizes the occurrence of the trajectory ripples.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.1-10
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• 2015

NAND flash systems require deletion operation and do not support in-place update, so the storage systems should use Flash Translation Layer (FTL). However, there are a lot of memory consumptions using mapping table in the FTL, so recently, many studies have been proposed to resolve mapping table overhead. These studies try to solve update propagation problem in the nand flash system which does not use mapping table. In this paper, we present a novel index structure, called CL-Tree(Cache List Tree), to solve the update propagation problem. The proposed index structure reduces write operations which occur for an update propagation, and it has a good performance for search operation because it uses multi-list structure. In experimental evaluation, we show that our scheme yields about 173% and 179% improvement in insertion speed and search speed, respectively, compared to traditional B+tree and other works.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.15-27
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• 2003

Recently, the volume of data is increasing rapidly in server for multimedia service, according to development of multimedia application environment. In recent research for storage technology the technology like of the SAN(Storage Area Network) advantages in scalibility of storage devices, and can read data from multiple disk arrays through RAID 0, 5. The RAID 0 and 5 translate to logical address to physical address using equation, but in case of adding disks at the system with equation -based mapping, the problem that we must rearrange the whole data in the previous disks happens. We use the mapping table to solve this problem in recent, but we can not load the whole mapping table in main memory because it occupies too large space. Therefore the extra I/Os are demanded to evaluate real physical address of data, so total performance of the system is degraded. In this paper, we propose the mapping method that supports the scalibility in RAID 0 or 5 system. The proposing method applies small metadata, so- called SZIT and simple equation, so it is possible that we make translate logical address to physical address rapidly and it is scalable in disk extending simultaneously Our suggesting method, if we add disks to the striping system for expanding of storage capacity, has an advantage of never stop service. So, SZlT-based mapping method can do online-disk-expanding in real-time service.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.5
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• pp.263-272
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• 2011

The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.

• Journal of the Korea Society of Computer and Information
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• v.27 no.12
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• pp.1-8
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• 2022

As an efficient file system for SSD(Solid State Drive), F2FS is employed in the kernel of Linux operating system. F2FS applies various methods to improve performance by reflecting the characteristics of flash memory. One of them is improvement of the index structure that contains addresses of data blocks for each file. This paper presents a method for further improving performance by modifying the index structure of F2FS. F2FS manages all index blocks as logical numbers, and an address mapping table is used to find the physical block addresses of index blocks on flash memory. This paper shows performance improvement by applying logical numbers to the last level index blocks only. The count of mapping table search for a data block access is reduced to 1~2 from 1~4.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.433-439
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• 2014

This paper proposes an architecture of two-stage string matching engine with content-addressable memory(CAM) and parallel bit-split string matchers for deep packet inspection(DPI). Each long signature is divided into subpatterns with the same length, where subpatterns are mapped onto the CAM in the first stage. The long pattern is matched in the second stage using the sequence of the matching indexes from the CAM. By adopting CAM and bit-split string matchers, the memory requirements can be greatly reduced in the heterogeneous string matching environments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.808-816
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• 2016

As the number of CPU/GPU cores and IPs in SOC increases and applications require explosive memory bandwidth, simultaneously achieving good throughput and fairness in the memory system among interfering applications is very challenging. Recent works proposed priority-based thread scheduling and channel partitioning to improve throughput and fairness. However, combining these different approaches leads to performance and fairness degradation. In this paper, we analyze the problems incurred when combining priority-based scheduling and channel partitioning and propose dynamic priority thread scheduling and adaptive channel partitioning method. In addition, we propose dynamic address mapping to further optimize the proposed scheme. Combining proposed methods could enhance weighted speedup and fairness for memory intensive applications by 4.2% and 10.2% over TCM or by 19.7% and 19.9% over FR-FCFS on average whereas the proposed scheme requires space less than TCM by 8%.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.