• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.177-187
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• 2000

In the past several years, many systems which adopted ring topology with high-speed unidirectional point-to-point links have emerged to overcome the limit of bus for interconnection network of clustered multiprocessor system. However, rapid increase of processor speed and performance improvement of local bus and memory system limit scalability of system with point-to-point link of standard bandwidth. Therefore, necessity to extend bandwidth is emphasized. In this paper, we adopt PANDA system as base model, which is clustering-based multiprocessor system. By simulating a model adopting commercial processor and local bus specification, we show that point-to-point link is bottleneck of system performance, and bandwidth expansion by more than 200% is needed. To expand bandwidth of interconnection network, it needs excessive design cost and time to develop new point-to-point link with doubled bandwidth. As an alternative to double bandwidth, we propose several ways to implement dual ring -simple dual ring, transaction-separated dual ring, direction-separated dual ring- by using off-the-shelf point-to-point links with IEEE standard bandwidth. We analyze pros. and cons. of each model compared with doubled-bandwidth single ring by simulation.

• Journal of KIISE
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• v.42 no.3
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• pp.307-319
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• 2015

Current ontology studies use the Hadoop distributed storage framework to perform map-reduce algorithm-based reasoning for scalable ontologies. In this paper, however, we propose a novel approach for scalable Web Ontology Language (OWL) Horst Lite ontology reasoning, based on distributed cluster memories. Rule-based reasoning, which is frequently used for scalable ontologies, iteratively executes triple-format ontology rules, until the inferred data no longer exists. Therefore, when the scalable ontology reasoning is performed on computer hard drives, the ontology reasoner suffers from performance limitations. In order to overcome this drawback, we propose an approach that loads the ontologies into distributed cluster memories, using Spark (a memory-based distributed computing framework), which executes the ontology reasoning. In order to implement an appropriate OWL Horst Lite ontology reasoning system on Spark, our method divides the scalable ontologies into blocks, loads each block into the cluster nodes, and subsequently handles the data in the distributed memories. We used the Lehigh University Benchmark, which is used to evaluate ontology inference and search speed, to experimentally evaluate the methods suggested in this paper, which we applied to LUBM8000 (1.1 billion triples, 155 gigabytes). When compared with WebPIE, a representative mapreduce algorithm-based scalable ontology reasoner, the proposed approach showed a throughput improvement of 320% (62k/s) over WebPIE (19k/s).

• KIISE Transactions on Computing Practices
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• v.21 no.12
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• pp.774-779
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• 2015

In this paper, we present the design and implementation of a large-scale qualitative spatial reasoner using Apache Spark, an in-memory high speed cluster computing environment, which is effective for sequencing and iterating component reasoning jobs. The proposed reasoner can not only check the integrity of a large-scale spatial knowledge base representing topological and directional relationships between spatial objects, but also expand the given knowledge base by deriving new facts in highly efficient ways. In general, qualitative reasoning on topological and directional relationships between spatial objects includes a number of composition operations on every possible pair of disjunctive relations. The proposed reasoner enhances computational efficiency by determining the minimal set of disjunctive relations for spatial reasoning and then reducing the size of the composition table to include only that set. Additionally, in order to improve performance, the proposed reasoner is designed to minimize disk I/Os during distributed reasoning jobs, which are performed on a Hadoop cluster system. In experiments with both artificial and real spatial knowledge bases, the proposed Spark-based spatial reasoner showed higher performance than the existing MapReduce-based one.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.10
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• pp.734-745
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• 2006

This paper presents a PC cluster-based distributed VOD server that minimizes the load of an interconnection network by adopting the VIA communication protocol and the interval cache algorithm. Video data is distributed to the disks of the distributed VOD server and each server node receives the data through the interconnection network and sends it to clients. The load of the interconnection network increases because of the large amount of video data transferred. This paper developed a distributed VOD file system, which is based on VIA, to minimize cost using interconnection network when accessing remote disks. VIA is a user-level communication protocol removing the overhead of TCP/IP. This papers also improved the performance of the interconnection network by expanding the maximum transfer size of VIA. In addition, the interval cache reduces traffic on the interconnection network by caching, in main memory, the video data transferred from disks of remote server nodes. Experiments using the distributed VOD server of this paper showed a maximum performance improvement of 21.3% compared with a distributed VOD server without VIA and the interval cache, when used with a four-node PC cluster.

• The Journal of the Korea Contents Association
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• v.15 no.4
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• pp.29-44
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• 2015

Digital Signage, a way of advertising or delivering information to viewers through digital displays, has expanded from being just an advertising channel in public places. Recently, it has become widely prevalent in restaurants and retail stores. Despite its wide expansion, digital signage is limited to specific usages and services and the devices it uses are also quite expensive. This study introduces a stick-type digital signage product that operates on Android OS, which addresses all the weaknesses of digital signage with much more reasonable pricing and stable operation. For stability, performance tests were executed on the hardware and applications. The results for hardware performance were extremely promising, as each scenario's maximum performance results, measured by Load Runner programs, reached target indexes. Also, as a result of the usability test, all participants, including non-digital signage system users (novices), were able to easily learn all the tasks. As a result of user satisfaction survey, positive responses were exhibited for ease of learning and usability (LEU), helpfulness and problem solving capabilities (HPSC), affective aspect and multimedia properties (AAMP), commands and minimal memory load (CMML), and control and efficiency (CE).

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.627-636
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• 2005

This paper presents a PC cluster-based distributed video on demand (VOD) server that minimizes the load of the interconnection network by adopting channel bonding-based MVIA and the interval cache algorithm Video data is distributed to the disks of each server node of the distributed VOD server and each server node receives the data through the interconnection network and sends it to clients. The load of the interconnection network increases because of the large volume of video data transferred. We adopt two techniques to reduce the load of the interconnection network. First, an Msupporting channel bonding technique is adopted for the interconnection network. n which is a user-level communication protocol that reduces the overhead of the TCP/IP protocol in cluster systems, minimizes the time spent in communicating. We increase the bandwidth of the interconnection network using the channel bonding technique with MThe channel bonding technique expands the bandwidth by sending data concurrently through multiple network cards. Second, the interval cache reduces traffic on the interconnection network by caching the video data transferred from the remote disks in main memory Experiments using the distributed VOD server of this paper showed a maximum performance improvement of $30\%$ compared with a distributed VOD server without channel bonding-based MVIA and the interval cache, when used with a four-node PC cluster.

• Korean Chemical Engineering Research
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• v.47 no.6
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• pp.715-719
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• 2009

The phase change electrode board for the bio-information detection through electrical property response of phase change material was developed in this study. We manufactured the electrode board using Aluminum first that is widely used in conventional semiconductor device process. Without further treatment, these aluminum electrodes tend to contain voids in PETEOS(plasma enhanced tetraethyoxysilane) material that are easily detected by cross-sectional SEM(Scanning Electron Microscope). The voids can be easily attacked and transformed into holes in between PETEOS and electrodes after etch back and washing process. In order to resolve this issue of Al electrode board, we developed a electrode board manufacturing method using low resistivity TiN, which has advantages in terms of the step-coverage of phase change($Ge_2Sb_2Te_5$, GST) thin film as well as thermodynamic stability, without etch back and washing process. This TiN material serves as the top and bottom electrode in PRAM(Phase-change Random Access Memory). The good connection between the TiN electrode and GST thin film was confirmed by observing the cross-section of TiN electrode board using SEM. The resistances of amorphous and crystalline GST thin film on TiN electrodes were also measured, and 1000 times difference between the amorphous and crystalline resistance of GST thin film was obtained, which is well enough for the signal detection.

• The KIPS Transactions:PartA
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• v.16A no.3
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• pp.159-168
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• 2009

In this paper, we present an efficient way of implementing OpenGL ES 1.1 standard for the environments with hardware-supported OpenGL API, such as desktop PCs. Although OpenGL ES was started from the existing OpenGL features, it becomes a new three-dimensional graphics library customized for embedded systems through introducing fixed-point arithmetic operations, buffer management with fixed-point data type supports, completely new texture mapping functionalities and others. Currently, it is the official three dimensional graphics library for Google Android, Apple iPhone, PlayStation3, etc. In this paper, we achieved improvements on the arithmetic operations for the fixed-point number representation, which is the most characteristic data type for OpenGL ES. For the conversion of fixed-point data types to the floating-point number representations for the underlying OpenGL, we show the way of efficient conversion processes even with satisfying OpenGL ES standard requirements. We also introduced a simple memory management scheme to mange the converted data for the buffer containing fixed-point numbers. In the case of texture processing, the requirements in both standards are quite different and thus we used completely new software-implementations. Our final implementation result of OpenGL ES library provides all of over than 200 functions in OpenGL ES 1.1 standard and completely passed its conformance test, to show its compliance with the standard. From the efficiency viewpoint, we measured its execution times for several OpenGL ES-specific application programs and achieved at most 33.147 times improvements, to become the fastest one among the OpenGL ES implementations in the same category.

• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.8 no.2
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• pp.273-286
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• 1997

Objective：This study was designed to evaluate effects of methylphenidate(MPH) on event-related potentials(ERP) and continuous performance test(CPT) in attention-deficit hyperactivity disorder (ADHD) and to see the correlation between changes in ERP and changes in performance. Method：ERP and CPT were used to examine the acute effects of MPH(0.5mg/kg) in eleven ADHD boys(89-103 months old). Results：1) After MPH administration, P3 latency to nontarget stimuli at Fz was significantly decreased (p<0.01) and P2 amplitudes to target stimuli at Pz and at Oz and P3 amplitude to target stimuli at Cz were significantly increased(p<0.05). 2) Commission error and omission error in the CPT-X and commission error in the CPT-AX were decreased(p<0.01), and hits and perceptual sensitivity(d') in the CPT-X and d′ in the CPT-AX were increased(p<0.01). 3) The change of P3 latency to nontarget stimuli at Fz and the change of d′ in the CPT-X were negatively correlated(p<0.05), and the change of P2 amplitude to target stimuli at Pz and d′ in the CPT-AX were positively correlated(p<0.05). Conclusion：MPH improves change orienting reaction, the delivery of task relevant information, accuracy and perceptual sensitivity in ADHD. And the increase of ability to discriminate targets from non-targets reflects reduced evaluation time in large memory component task and enhanced change orienting reaction in simple task.