• The Transactions of the Korea Information Processing Society
• /
• v.3 no.4
• /
• pp.947-960
• /
• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• Journal of Information Technology Applications and Management
• /
• v.11 no.2
• /
• pp.29-43
• /
• 2004

As the development of an information technique, gradually, mobile device is going to be miniaturized and operates at high speed. By such the requirements, the devices using a flash memory as a storage media are increasing. The flash memory consumes low power, is a small size, and has a fast access time like the main memory. But the flash memory must erase for recording and the erase cycle is limited. JFFS is a representative filesystem which reflects the characteristics of the flash memory. JFFS to be consisted of LSF structure, writes new data to the flash memory in sequential, which is not related to a file size. Mounting a filesystem or an error recovery is achieved through the sequential approach. Therefore, the mounting delay time is happened according to the file system size. This paper proposes a MJFFS to use a multi-checkpoint information to manage a mass flash file system efficiently. A MJFFS, which improves JFFS, divides a flash memory into the block for suitable to the block device, and stores file information of a checkpoint structure at fixed interval. Therefore mounting and error recovery processing reduce efficiently a number of filesystem access by collecting a smaller checkpoint information than capacity of actual files. A MJFFS will be suitable to a mobile device owing to accomplish fast mounting and error recovery using advantage of log foundation filesystem and overcoming defect of JFFS.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.7
• /
• pp.789-793
• /
• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• Korean Journal of Cognitive Science
• /
• v.23 no.4
• /
• pp.487-515
• /
• 2012

The purpose of this study was to investigate the effect of the individual differences in cognitive processes on paragraph comprehension. To do so, the lexical decision task and the pattern comparison task were used to measure the low-level cognitive processes. Digit span task was used to test the phonological loop capacity. The individual differences of the central executive processing capacity were measured by operational span task. Reading span task was used to test the working memory capacity related with the sentence processing. Reading times and accuracies of the logically valid inferences and logically void inferences were tested to measure the high-level cognitive processes. Reading times and accuracies for the target sentences with and without prior explicit causal sentence were measured to test individuals' paragraph comprehension abilities. The results showed that the speed of the low-level cognitive processes was related with the speed of the high-level cognitive processes. Also, the accuracy of the low-level cognitive processes was related with the accuracy of the high-level cognitive processes while there was no significant correlation between the speed and the accuracy in any measures of the cognitive processes. Working memory capacity was related with the accuracy of the cognitive processes while it was not significantly correlated with the speed of the cognitive processes. Most importantly, the speed of low-level cognitive processes significantly affected the speed of the paragraph comprehension while the working memory capacity and the high-level cognitive processes had influences on the accuracies of the paragraph comprehension. The speed of the paragraph comprehension had no influence on the accuracies of the paragraph comprehension.

• Toxicological Research
• /
• v.31 no.4
• /
• pp.347-354
• /
• 2015

Excess manganese (Mn) is neurotoxic. Increased manganese stores in the brain are associated with a number of behavioral problems, including motor dysfunction, memory loss and psychiatric disorders. We previously showed that the transport and neurotoxicity of manganese after intranasal instillation of the metal are altered in Hfe-deficient mice, a mouse model of the iron overload disorder hereditary hemochromatosis (HH). However, it is not fully understood whether loss of Hfe function modifies Mn neurotoxicity after ingestion. To investigate the role of Hfe in oral Mn toxicity, we exposed Hfe-knockout ($Hfe^{-/-}$) and their control wild-type ($Hfe^{+/+}$) mice to $MnCl_2$ in drinking water (5 mg/mL) for 5 weeks. Motor coordination and spatial memory capacity were determined by the rotarod test and the Barnes maze test, respectively. Brain and liver metal levels were analyzed by inductively coupled plasma mass spectrometry. Compared with the water-drinking group, mice drinking Mn significantly increased Mn concentrations in the liver and brain of both genotypes. Mn exposure decreased iron levels in the liver, but not in the brain. Neither Mn nor Hfe deficiency altered tissue concentrations of copper or zinc. The rotarod test showed that Mn exposure decreased motor skills in $Hfe^{+/+}$ mice, but not in $Hfe^{-/-}$ mice (p = 0.023). In the Barns maze test, latency to find the target hole was not altered in Mn-exposed $Hfe^{+/+}$ compared with water-drinking $Hfe^{+/+}$ mice. However, Mn-exposed $Hfe^{-/-}$ mice spent more time to find the target hole than Mn-drinking $Hfe^{+/+}$ mice (p = 0.028). These data indicate that loss of Hfe function impairs spatial memory upon Mn exposure in drinking water. Our results suggest that individuals with hemochromatosis could be more vulnerable to memory deficits induced by Mn ingestion from our environment. The pathophysiological role of HFE in manganese neurotoxicity should be carefully examined in patients with HFE-associated hemochromatosis and other iron overload disorders.

• Journal of Convergence for Information Technology
• /
• v.11 no.11
• /
• pp.44-50
• /
• 2021

Recently, enterprise storage systems that require large-capacity storage devices to accommodate big data have used large-capacity flash memory-based storage devices with high density compared to cost and size. This paper proposes a high-efficiency life prediction method with slope descent to maximize the life of flash memory media that directly affects the reliability and usability of large enterprise storage devices. To this end, this paper proposes the structure of a matrix for storing metadata for learning the frequency of defects and proposes a cost model using metadata. It also proposes a life expectancy prediction policy in exceptional situations when defects outside the learned range occur. Lastly, it was verified through simulation that a method proposed by this paper can maximize its life compared to a life prediction method based on the fixed number of times and the life prediction method based on the remaining ratio of spare blocks, which has been used to predict the life of flash memory.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.1016-1021
• /
• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Steel and Composite Structures
• /
• v.26 no.2
• /
• pp.213-226
• /
• 2018

This paper focuses on the seismic protection of slender old masonry structures by the implementation of prestressing devices at key locations. The devices are vertically and externally located inside the towers in order to be reversible and calibrated. An extensive parametric study on a selected slender tower is carried out based on more than 100 nonlinear static simulations aimed at investigating the impact of different parameters on the seismic performance: (i) different prestressing levels; (ii) shape memory alloy superelasticity and (iii) changes in prestressing-forces in all the stages of the analysis until failure and masonry toe crushing. The tendon materials under analysis are conventional prestressing steel, fiber-reinforced polymers of different fibers and shape memory alloys. The parametric study serves to select the most suitable prestressing device and optimal prestressing level able to dissipate more earthquake energy. The seismic energy dissipation is evaluated by comparing the structural capacity curves in original state and retrofitted.

• Transactions of the Society of Information Storage Systems
• /
• v.1 no.1
• /
• pp.1-22
• /
• 2005

There are two important trends in the modern information society, including digital networking and ubiquitous environment. Thus it is strongly required to develop new information storage devices such as high density storages to match the increased data capacity and small size storage devices to be applied to the mobile multimedia electronics. So far, many approaches have been studied for the high density memory, including the holographic memory, super-RENS and near-field recording using solid immersion lens (SIL) or nano-probe for the ODD (Optical Disk Drive) system, and the perpendicular magnetic recording and heat-assisted magnetic recording for the HDD (Hard Disk Drive) system. In addition, new mobile storage devices have been prepared using 0.85" HDD and 30mm ODD systems from a lot of foreign and domestic companies and institutes. In this paper, the recent technology trend for the next generation information storage system is summarized to offer a research motivation and encouragement to new researchers in this field with an emphasis on the technical issues of the increase of data capacity and decrease of device size.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.31-32
• /
• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]