• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.7 s.250
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• pp.787-793
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• 2006

Recently kriging model has been widely used in the DACE (Design and Analysis of Computer Experiment) because of prominent predictability of nonlinear response. Since DACE has no random or measurement errors contrast to physical experiment, space filling experimental design that distributes uniformly design points over whole design space should be employed as a sampling method. In this paper, we examine the maximum entropy experimental design that reveals the space filling strategy in which defines the maximum entropy based on Gaussian or exponential. The influence of these two correlation functions on space filling design and their model parameters are investigated. Based on the exploration of numerous numerical tests, enhanced maximum entropy design based on exponential correlation function is suggested.

• Journal of Information Processing Systems
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• v.11 no.2
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• pp.248-265
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• 2015

In this paper, we propose a maximum entropy-based model, which can mathematically explain the bio-molecular event extraction problem. The proposed model generates an event table, which can represent the relationship between an event trigger and its arguments. The complex sentences with distinctive event structures can be also represented by the event table. Previous approaches intuitively designed a pipeline system, which sequentially performs trigger detection and arguments recognition, and thus, did not clearly explain the relationship between identified triggers and arguments. On the other hand, the proposed model generates an event table that can represent triggers, their arguments, and their relationships. The desired events can be easily extracted from the event table. Experimental results show that the proposed model can cover 91.36% of events in the training dataset and that it can achieve a 50.44% recall in the test dataset by using the event table.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.