• Title/Summary/Keyword: Master Block

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Dynamic mechanism of rock mass sliding and identification of key blocks in multi-fracture rock mass

  • Jinhai Zhao;Qi Liu;Changbao Jiang;Zhang Shupeng;Zhu Weilong;Ma Hailong
    • Geomechanics and Engineering
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    • v.32 no.4
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    • pp.375-385
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    • 2023
  • There are many joint fissures distributed in the engineering rock mass. In the process of geological history, the underground rock mass undergoes strong geological processes, and undergoes complex geological processes such as fracture breeding, expansion, recementation, and re-expansion. In this paper, the damage-stick-slip process (DSSP), an analysis model used for rock mass failure slip, was established to examine the master control and time-dependent mechanical properties of the new and primary fractures of a multi-fractured rock mass under the action of stress loading. The experimental system for the recemented multi-fractured rock mass was developed to validate the above theory. First, a rock mass failure test was conducted. Then, the failure stress state was kept constant, and the fractured rock mass was grouted and cemented. A secondary loading was applied until the grouted mass reached the intended strength to investigate the bearing capacity of the recemented multi-fractured rock mass, and an acoustic emission (AE) system was used to monitor AE events and the update of damage energy. The results show that the initial fracture angle and direction had a significant effect on the re-failure process of the cement rock mass; Compared with the monitoring results of the acoustic emission (AE) measurements, the master control surface, key blocks and other control factors in the multi-fractured rock mass were obtained; The triangular shaped block in rock mass plays an important role in the stress and displacement change of multi-fracture rock mass and the long fissure and the fractures with close fracture tip are easier to activate, and the position where the longer fractures intersect with the smaller fractures is easier to generate new fractures. The results are of great significance to a multi-block structure, which affects the safety of underground coal mining.

EFFECTS OF DIFFERENT PREPARATION METHODS ON THE MORPHOLOGIC CHANGE OF SIMULATED ROOT CANALS IN RESIN BLOCK (수종 근관형성방법에 따른 레진모형상의 근관형태의 변화)

  • Park, Mi-Hee;Hong, Chan-Ui
    • Restorative Dentistry and Endodontics
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    • v.19 no.1
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    • pp.85-96
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    • 1994
  • In this study, 24 curved resin blocks were prepared by one of the following four methods: 1) Conventional technique using K-flexo files 2) Step-back technique using K-flexo files 3) Crown-down technique using K-flexo files 4) Canal Master instrumentation using Canal Master Resin blocks were sectioned, photographed, and evaluated the mean centering ratio and the mean area of dentin removed before and after the instrumentation. The results were as follows : I. the mean centering ratio 1. In the level 1 and level 3, there was no significant difference in the mean centering ratio. 2. In the level 2, Step-back technique showed the worst mean centering ratio among the tested groups(p<0.001) and there was no significant difference between the other three groups. 3. In the level 4, Canal Master instrumentation and Step-back technique showed better mean centering ratio than the other two techniques(p<0.001) and there was no significant difference between the two techniques. II. the mean area of dentin removed 1. In the level l and level 3, there was no significant difference in the mean area of dentin removed. 2. In the level 2, Canal Master instrumentation removed less dentin than the other three techniques(P<0.01). 3. In the level 4, Crown-down technique removed less dentin than the other three techniques(P<0.05).

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A Study on the Jacket Blocks for Adult Males according to their Somatotypes XS, YI, Yd, and AD2

  • Jung, Jae-Eun
    • Journal of Fashion Business
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    • v.12 no.3
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    • pp.136-152
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    • 2008
  • The purpose of this study was to provide dress forms and jacket blocks for adult males based on the analysis of their somatotypes. As the result of the research conducted for this study that was based on 1290 males of 20 to 54 years-old, the shapes of adult male were 20 and each body shape was classified by size factor, height and chest girth. Also, master sizes were selected considering appearance frequency. XS type (master size: height 165cm and chest circumference 88cm), Yd type (master size: height 170cm and chest circumference 91cm), YI and AD2 types (master size: height 170cm and chest circumference 94cm) were selected to develop dress forms and their jacket blocks in this study. The procedure and results were follows; 1. The dress forms of XS, Yd, YI and AD2 types were produced base on means of 61 body measurements and cross sections of shoulder, chest, waist, hip of subjects belong to each somatotype. 2. New jacket blocks for XS, Yd, YI and AD2 types were developed based on the body surface developments through draping and the results of comparative investigation on the existing jacket blocks by wearing test. Also the drafting methods of new jacket blocks were provided. 3. The sensory evaluation by wearing test showed that the developed jacket blocks were estimated more highly in terms of chest's allowance, the front width's allowance, neck wrinkle, front allowance and overall appearance's fitness items than existing jacket blocks.

Design of a 3GPP LTE system Information(MIB) detection simulator (3GPP LTE 시스템정보(MIB) 추출에 대한 연구)

  • Gwag, Gyoung-Hun;Oh, Hyuk-Jun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.827-829
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    • 2015
  • This paper presents process of the UE obtains the cell system information in order to achieve communication with the LTE network on the LTE. This paper deals with the process of extracting MIB(Master Information Block) cell system information in LTE. To study the 3GPP LTE standard spec series 36.200 and 36.300, the simulation is implemented to extract the MIB in MATLAB program. The simulation process is divided into three parts. It consisted of a part that extracts the PSS, SSS and MIB. Called a cell search process for detecting the PSS and SSS, the process is to be done in order to extract only the cell system information. The simulation program is verified based on the signal captured from the real Air.

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Differential Power Analysis Attack of a Block Cipher ARIA (블럭 암호 ARIA에 대한 차분전력분석공격)

  • Seo JungKab;Kim ChangKyun;Ha JaeCheol;Moon SangJae;Park IlHwan
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.15 no.1
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    • pp.99-107
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    • 2005
  • ARIA is a 128-bit block cipher having 128-bit, 192-bit, or 256-bit key length. The cipher is a substitution and permutation encryption network (SPN) and uses an involutional binary matrix. This structure was efficiently developed into light weight environments or hardware implementations. This paper shows that a careless implementation of an ARIA on smartcards is vulnerable to a differential power analysis attack This attack is realistic because we can measure power consumption signals at two kinds of S-boxes and two types of substitution layers. By using the two round key, we extracted the master key (MK).

An Efficient Hardware Implementation of Lightweight Block Cipher LEA-128/192/256 for IoT Security Applications (IoT 보안 응용을 위한 경량 블록암호 LEA-128/192/256의 효율적인 하드웨어 구현)

  • Sung, Mi-Ji;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.7
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    • pp.1608-1616
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    • 2015
  • This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

Improved Impossible Differential Attack on 7-round Reduced ARIA-256

  • Shen, Xuan;He, Jun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.11
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    • pp.5773-5784
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    • 2019
  • ARIA is an involutory SPN block cipher. Its block size is 128-bit and the master key sizes are 128/192/256-bit, respectively. Accordingly, they are called ARIA-128/192/256. As we all know, ARIA is a Korean Standard block cipher nowadays. This paper focuses on the security of ARIA against impossible differential attack. We firstly construct a new 4-round impossible differential of ARIA. Furthermore, based on this impossible differential, a new 7-round impossible differential attack on ARIA-256 is proposed in our paper. This attack needs 2118 chosen plaintexts and 2210 7-round encryptions. Comparing with the previous best result, we improve both the data complexity and time complexity. To our knowledge, it is the best impossible differential attack on ARIA-256 so far.

Design and Implementation of Hangul Outline Font Generation Accelerator (한글 외곽선 글자체 생성 가속기의 설계 및 구현)

  • 배종홍;황규철;이윤태;경종민
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.2
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    • pp.100-106
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    • 1992
  • In this pape, we designed and implemented a hardware accelerator for the generation of bit map font from Hangul outline font description for LBP (Laser Beam Printer) and screen applications Whole system was implemented as a double size PC/AT application board which consists of processing bolck and display block. The processing block has a master processor (MC68000)and two slave processors which are MC56001 and KAFOG chip responsible for the short vector generation. In the display block, TMS34061 was used for monitor display and GP425 was used for LBP print out. The resolution of the monitor is 640$\times$480 and that of LBP is 2385$\times$3390. The current system called KHGB90-B generates about 100 characters per second where each character consists of 32$\times$32 bits

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Design and Implementation of Image Segmentation Tx/Rx Technology Based On BLE(Bluetooth Low Energy) Multiple Access Technology for Image Block Devices (이미지 블록 디바이스를 위한 BLE 다중 접속기술 기반 이미지 분할 송수신 기술의 설계 및 구현)

  • Kwak, Chang-Sub;Lee, Young-Soon
    • Journal of Korea Multimedia Society
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    • v.24 no.6
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    • pp.825-837
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    • 2021
  • The Bluetooth Low Energy profile has the advantage of continuing wireless communication with very little power consumption compared to the existing Bluetooth, so it is widely applied to smart devices. Most of them are applied to Point-to-Point (1:1) communication between Central (Master) and Peripheral (Slave), but can be applied to Point-to-Multiple (1:N) wireless communication through the use of multiple threads and timers. Therefore, in this paper, a precise timer was designed in the BLE profile to devise an image segmentation transmission/reception structure based on multiple access, and a smart image block device applied to it was designed and verified.

A Hardware Implementation of Ultra-Lightweight Block Cipher PRESENT-80/128 (초경량 블록암호 PRESENT-80/128의 하드웨어 구현)

  • Cho, Wook-Lae;Kim, Ki-Bbeum;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.430-432
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    • 2015
  • This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

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