• The KIPS Transactions:PartD
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• v.12D no.4 s.100
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• pp.543-552
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• 2005

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. The disk-based spatial indexing techniques, however, cannot direct apply to main memory databases, because the main purpose of disk-based techniques is to reduce the number of disk accesses. In main memory-based indexing techniques, the node access time is much faster than that in disk-based indexing techniques, because all index nodes reside in a main memory. Unlike disk-based index techniques, main memory-based spatial indexing techniques must reduce key comparing time as well as node access time. In this paper, we propose an efficient spatial index structure for main memory-based databases, called Tmr-tree. Tmr-tree integrates the characteristics of R-tree and T-tree. Therefore, Nodes of Tmr-tree consist of several entries for data objects, main memory pointers to left and right child, and three additional fields. First is a MBR of a self node, which tightly encloses all data MBRs (Minimum Bounding Rectangles) in a current node, and second and third are MBRs of left and right sub-tree, respectively. Because Tmr-tree needs not to visit all leaf nodes, in terms of search time, proposed Tmr-tree outperforms R-tree in our experiments. As node size is increased, search time is drastically decreased followed by a gradual increase. However, in terms of insertion time, the performance of Tmr-tree was slightly lower than R-tree.

• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.367-377
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• 1999

Nowadays, the number of database applications which need fast transaction processing are increasing. One way to improve the performance of transaction processing is to reside the whole database in main memory As semiconductor memory becomes cheaper and chip densities increase, the research to improve transaction throughput rates of transaction processing system, using main memory databases, has begun In this thesis, how to implement a high performance transaction processing system based on main memory databases, new concurrency control scheme, recovery scheme and storage structure is presented. The objective of the proposed schemes is to improve the transaction processing system performance measured by transaction throughput and response times.

• KIISE Transactions on Computing Practices
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• v.22 no.8
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• pp.363-368
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• 2016

A storage-based VDI (Virtual Desktop Infrastructure) system has the disadvantage of degraded performance when IOs for the VDI system are concentrated on the storage. The performance of the VDI system decreases rapidly especially, in case of the boot storm wherein all virtual desktops boot simultaneously. In this paper, we propose a main memory-based virtual desktop system managing virtual desktop images on main memory to solve the performance degradation problem including the boot storm. Performance of the main memory-based VDI system is improved by storing the virtual desktop image on the main memory. Also, the virtual desktop images with large size can be stored in the main memory using deduplication technology. Implementation of the proposed VDI system indicated that it has 4 times performance benefit than the storage-based VDI system in case of the boot storm.

• Journal of KIISE
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• v.42 no.2
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• pp.183-189
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• 2015

Recently, computer systems have encountered difficulties in making further progress due to the technical limitations of DRAM based main memory technologies. This has motivated the development of next generation memory technologies that have high density and non-volatility. However, these new memory technologies also have their own intrinsic limitations, making it difficult for them to currently be used as main memory. In order to overcome these problems, we propose a hybrid main memory system, namely HyMN, which utilizes the merits of next generation memory technologies by combining two types of memory: Write-Affable RAM(WAM) and Read-Affable RAM(ReAM). In so doing, we analyze the appropriate WAM size for HyMN, at which we can avoid the performance degradation. Further, we show that the execution time performance of HyMN, which provides an additional benefit of durability against unexpected blackouts, is almost comparable to legacy DRAM systems under normal operations.

• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.673-676
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• 2004

To manage and query moving objects efficiently in MMDBMS, a memory index structure should be used. The most popular index structure for storing trajectories of moving objects is 3DR-tree. The 3DR-tree also can be used for MMDBMS. However, the volume of data can exceed the capacity of physical memory since moving objects report their locations continuously. To accommodate new location reports, old trajectories should be migrated to disk or purged from memory. This paper focuses on migration policies of a main memory index structure. Migration policies consist of two steps: (i) node selection, (ii) node placement. The first step (node selection) selects nodes that should be migrated to disk. The criteria of selection are the performance of insertion or query. The second step (node placement) determines the order of nodes written to disk. This step can be thought as dynamic declustering policies.

• International Journal of Contents
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• v.3 no.3
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• pp.1-5
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• 2007

The main memory DBMS (MMDBMS) efficiently supports various database applications that require high performance since it employs main memory rather than disk as a primary storage. An index manager is an essential sub-component of a DBMS used to speed up the retrieval of objects from a large volume of a database in response to a certain search condition. Previous research efforts on indexing proposed various index structures. However, they hardly dealt with the practical issues occurred in implementing an index manager on a target DBMS. In this paper, we touch these issues and present our experiences in developing the index manager. The main issues are (1) compact representation of an index entry, (2) support of variable-length keys. (3) support of multiple-attribute keys, and (4) support of duplicated keys.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• The KIPS Transactions:PartD
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• v.11D no.1
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• pp.11-22
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• 2004

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. Consequently, reducing cache misses emerges as the most important issue in current main memory databases, in which CPU speeds have been increasing at 60% per year, compared to the memory speeds at 10% per you. In this paper, we design and implement a main-memory database system for real-time mobile GIS. Our system is composed of 5 modules： the interface manager provides the interface for PDA users； the memory data manager controls spatial and non-spatial data in main-memory using virtual memory techniques； the query manager processes spatial and non-spatial query : the index manager manages the MR-tree index for spatial data and the T-tree index for non-spatial index : the GIS server interface provides the interface with disk-based GIS. The MR-tree proposed propagates node splits upward only if one of the internal nodes on the insertion path has empty space. Thus, the internal nodes of the MR-tree are almost 100% full. Our experimental study shows that the two-dimensional MR-tree performs search up to 2.4 times faster than the ordinary R-tree. To use virtual memory techniques, the memory data manager uses page tables for spatial data, non- spatial data, T-tree and MR-tree. And, it uses indirect addressing techniques for fast reloading from disk.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.125-134
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• 2004

Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.188-193
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• 2022

The energy efficiency of memory systems is an important task in designing future computer systems as memory capacity continues to increase to accommodate the growing big data. In this article, we present an energy-efficient last-level cache management policy for future mobile systems. The proposed policy makes use of low-power PCM (phase-change memory) as the main memory medium, and reduces the amount of data written to PCM, thereby saving memory energy consumptions. To do so, the policy keeps track of the modified cache lines within each cache block, and replaces the last-level cache block that incurs the smallest PCM writing upon cache replacement requests. Also, the policy considers the access bit of cache blocks along with the cache line modifications in order not to degrade the cache hit ratio. Simulation experiments using SPEC benchmarks show that the proposed policy reduces the power consumption of PCM memory by 22.7% on average without degrading performances.