• Title/Summary/Keyword: MUT(Memory Under Test)

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A Parallel Test Structure for eDRAM-based Tightly Coupled Memory in SoCs (시스템 온 칩 내 eDRAM을 사용한 Tightly Coupled Memory의 병렬 테스트 구조)

  • Kook, In-Sung;Lee, Jae-Min
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.3
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    • pp.209-216
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    • 2011

  • Recently the design of SoCs(System-on-Chips) in which TCM is embedded for high speed operation increases rapidly. In this paper, a parallel test structure for eDRAM-based TCM embedded in SoCs is proposed. In the presented technique, the MUT (Memory Under Test) is changed to parallel structure and it increases testability of MUT with boundary scan chains. The eDRAM is designed in structure for parallel test so that it can be tested for each modules. Dynamic test can be performed based on input-output data. The proposed techniques are verified their performance by circuits simulation.

  • https://doi.org/10.17661/jkiiect.2011.4.3.209 인용 PDF