• 제목/요약/키워드: MTPL

검색결과 2건 처리시간 0.017초

효율적 코드변환 알고리즘에 기반한 PLC 의 체계적 설계 (Systematic Design of Programmable Logic Controller Based on Efficient Code Conversion Algorithm)

  • 차종호;조광현
    • 제어로봇시스템학회논문지
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    • 제7권12호
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    • pp.1009-1014
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    • 2001
  • The ladder diagram (LD) for programmable logic controllers (PLCs) ar responsible for much important roles in advance industrial automation. As automated systems become more complex the design procedures of the system become more difficult as well. Hence. the design automation issues based on discrete event models(DEMs) are receiving more attention. One of the popular ways of tackling these problems is employing Petri nets. In this paper, we use the modified automation Petri net(MAPN) to model the manufacturing system and the modified token passing logic (MTPL) method conversion (ECC) algorithm based on the MAPN and the MTPL Finally, an example of the manufacturing system is provided to illustrate the proposed ECC algorithm.

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DDR 알고리즘에 기반한 교착상태배제 래더 다이어그램 설계 (Synthesis of Deadlock-Free Ladder Diagrams for PLCs Based on Deadlock Detection and.Recovery (DDR) Algorithm)

  • 차종호;조광현
    • 제어로봇시스템학회논문지
    • /
    • 제8권8호
    • /
    • pp.706-712
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    • 2002
  • In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.