• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.102-107
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• 1996

Use of a rapid thermal annealing (RTA) technique is shown to improve the properties of metal-ferroelectric BaMgF$_{4}$-silicon structures. The fluoride film was deposited in an ultra-high vacuum system at asubstrate temperature of 300$^{\circ}C$. A post-deposition annelaing was conducted for 10 seconds at 600.deg. C in a vacuum of 0.1 Torr, using a home-made RTA apparatus. The results showed that the resistivity of the ferroelectric BaMgF$_{4}$ film from a typical value of 1-2${\times}10^{11}{\Omega}{\cdot}cm$ before the annealing to about 5${\times}10^{13}{\Omega}{\cdot}cm$ and reduce the interface state density of the BaMgF$_{4}$/Si interface to about 8${\times}10^{10}cm^{2}{\cdot}$eV. Ferroelectric hysteresis measurements using a sawyer-tower circuit yielded remanent polarization and coercive field values of about 0.5$\mu$C/cm$^{2}$ and 80 kV/cm, respectively. the typical remanent polarization of the BaMgF$_{4}$ films ont he (100) and (111) oreientated silicon wafers were 0.5 - 0.6 $\mu$C/cm$^{2}$ and that of th efilms on the (110) wafers was 1.2$^{\circ}C$/cm$^{2}$.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1029-1033
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• 1997

A prototype MFSFET using ferroelectric fluoride BaMgF$_4$as a gate insulator has been successfully fabricated with the help of 2 sheets of metal mask. The fluoride film was deposited in an ultrai-high vacuum system at a substrate temperature of below 30$0^{\circ}C$ and an in-situ post-deposition annealing was conducted for 20 seconds at $650^{\circ}C$ in the same chamber. The interface state density of the BaMgF$_4$/Si(100) interface calculated by a MFS capacitor fabricated on the same wafer was about 8$\times$10$^{10}$ /cm$^2$.eV. The I$_{D}$-V$_{G}$ characteristics of the MFSFET show a hysteresis loop due to the ferroelectric nature of the BaMgF$_4$film. It is also demonstrated that the I$_{D}$ can be controlled by the “write” plus which was applied before the measurements even at the same “read”gate voltage.ltage.

• International Journal of High-Rise Buildings
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• v.9 no.4
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• pp.307-314
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• 2020

High-rise buildings with vertical setback are widely used in practice. From the field investigation of the past earthquakes, it was found that such kind of vertically irregular high-rise building structures easily suffer severe damage during strong earthquakes. This paper presents an extensive study on the earthquake responses of moment-resisting frame structures (MFS) popularly applied in high-rise buildings with vertical setback. Four groups of MFS are designed, including three groups of structures with vertical setback and one group of structures with the lateral stiffness varying along the building height but without vertical setback. The numerical models of the structures are established, and the time history analysis of the structures under different levels of earthquakes is conducted. The earthquake responses of the structures are compared. The influence of the ratio between the horizontal setback dimension and the previous plan dimension, the eccentricity of setback, and the position where the setback occurs on the seismic performance of structures is studied. The rationality of the provisions for the structures with vertical setback specified in the current design codes is checked by the findings from this study.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• Journal of the Korean Vacuum Society
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• v.9 no.4
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• pp.315-320
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• 2000

We have investigated the crystal structure and electrical properties of Pt/SBT/$ZrO_2$/Si (MFIS) and Pt/SBT/Si (MFS) structures for the gate oxide of ferroelectric memory. XRD spectra and SEM showed that the SBT film of SBT/$ZrO_2$/Si structure had larger grain than that of SBT/Si structure. $ZrO_2$ film between SBT film and Si substrate is confirmed as a good candidate for a diffusion barrier by the analysis of AES. The remanent polarization decreased and coercive voltage increased in Pt/SBT/$ZrO_2$/Pt/$SiO_2$/Si structure. This effect may increase memory window of MFIS structure directly related to the coercive voltage. From the capacitance-volt-age characteristics, the memory windows of Pt/SBT (210 nm)/$ZrO_2$ (28 nm)/Si structure were in the range of 1~l.5 V at the applied voltage of 4~6 V. The current densities of Pt/SBT/ZrO$_2$/Si with as -deposited Pt electrode and annealed at $800^{\circ}C$ in $O_2$ambient were $8\times10^{-8} A/\textrm{cm}^2$ and $4\times10^{-8}A/\textrm{cm}^2$ , respectively.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2873-2875
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• 2005

The optimal structure of the conventional Fuzzy Polynomial Neural Networks (FPNN)[3] depends on experience of designer. For the conventional Fuzzy Polynomial Neural Networks, input variable number, number of input variable, number of Membership Functions(MFs) and consequence structures are selected through the experience of a model designer iteratively. In this paper, we propose the new design methodology to find the optimal structure of Fuzzy Polymomial Neural Network by using Genetic Algorithms(GAs)[4, 5]. In the sequel, It is shown that the proposed Advanced Genetic Algorithms based Fuzzy Polynomial Neural Network(Advanced GAs-based FPNN) is more useful and effective than the existing models for nonlinear process. We used Medical Imaging System(MIS)[6] data to evaluate the performance of the proposed model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.20-21
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• 2008

Ferroelectric vinylidene fluoride-trifluoroethylene ($VF_2$-TrFE) copolymer films were directly deposited on degenerated Si ($n^+$, 0.002 $\Omega{\cdot}cm$) using by dip coating method. A 1 ~ 3 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene ($VF_2$:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers using dip coating method for 10 seconds. After Post-Annealing in a vacuum ambient at 100~200 $^{\circ}C$ for 60 min, upper aluminum electrodes were deposited by thermal evaporation through the shadow mask to complete the MFS structure. The ferroelectric $\beta$-phase peak of films, depending on the annealing temperature, started to show up around $125^{\circ}C$, and the intensity of the peak increased with increasing annealing temperature. Above $175^{\circ}C$, the peak started to decrease. The C-V characteristics were measured using a Precision LCR meter (HP 4284A) with frequency of 1MHz and a signal amplitude of 20 mV. The leakage-current versus electric-field characteristics was measured by mean of a pA meter/DC voltage source (HP 4140B).

• ETRI Journal
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• v.20 no.2
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• pp.241-249
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• 1998

The structure and electrical characteristics of metal-ferroelectric-semiconductor FET(MFSFET) for a single transistor memory are presented. The MFSFET was comprised of polysilicon islands as source/drain electrodes and $BaMgF_4$ film as a gate dielectric. The polysilicon source and drain were built-up prior to the formation of the ferroelectric film to suppress a degradation of the film due to high thermal cycles. From the MFS capacitor, the remnant polarization and coercive field were measured to be about $0.6{\mu}C/cm^2$ and 100 kV/cm, respectively. The fabricated MFSFETs also showed good hysteretic I-V curves, while the current levels disperse probably due to film cracking or bad adhesion between the film and the Al electrode.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.270-272
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• 2006

In this paper, we discuss optimal design of Fuzzy Polynomial Neural Networks by means of Genetic Algorithms(GAs) using symbolic coding for non-linear data. One of the major subject of genetic algorithms is representation of chromosomes. The proposed model optimized by the means genetic algorithms which used symbolic code to represent chromosomes. The proposed gFPNN used a triangle and a Gaussian-like membership function in premise part of rules and design the consequent structure by constant and regression polynomial (linear, quadratic and modified quadratic) function between input and output variables. The performance of the proposed model is quantified through experimentation that exploits standard data already used in fuzzy modeling. These results reveal superiority of the proposed networks over the existing fuzzy and neural models.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.115-116
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• 2008

The ferroelectric vinylidene fluoride-trifluoroethylene ($VF_2$-TrFE) and $Al_2O_3$ passivation layer for the Metal/Insulator/Ferroelectric/Semiconductor (MIFS) structure were deposited using spin coating and remote plasma atomic layer deposition (RPALD), respectively. A 2.5 ~ 3 wt % diluted solution of purified vinylidene fluoride-trifluoroethylene ($VF_2$: TrFE=70:30) in a DMF solution were prepared and deposited on silicon wafer at a optimized spin speed. After annealing in a vacuum ambient at 150 ~ $200^{\circ}C$ for 60 min, upper insulator layer were deposited at temperature ranging from 100 ~ $150^{\circ}C$ by RPALD. We described electrical and structural properties of MIFS fabricated by spin coating and RPALD methods.