• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.221-225
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• 2003

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.128-129
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• 2007

We fabricated seeded $SrBi_2Ta_2O_9$(SBT) thin films using seeding technique on the $LaZrO_x$ (LZO)/Si structure. To evaluate the ferroelectric properties of seeded SBT thin films, we investigated the crystalline phase, the surface morphology, the capacitance-voltage (C-V) curve and the current density-voltage (J-V) curve of seeded films and then compared with the physical and electrical properties of unseeded films. As the result of that, the characteristics of seeded and unseeded films have a slight difference. Therefore, the ferroelectric properties of seeded SBT thin films are not necessarily superior than unseeded films.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.172-173
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• 2006

Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.734-737
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• 2004

The metal-ferroelectric-semiconductor (MFS) structure is widely studied for nondestructive readout (NDRO) memory devices, but conventional MFS structure has a critical problem. It is difficult to obtain ferroelectric films like PZT on Si substrate without interdiffusion of impurities such as Pb, Ti and other elements. In order to solve these problems, the metal-ferroelectric-insulator-semiconductor (MFIS) structure has been proposed with a buffer layer of high dielectric constant such as MgO, $Y_2O_3$, and $CeO_2$. In this study, the etching characteristics (etch rate, selectivity) of MgO thin films were etched using $Cl_2/Ar$ plasma. The maximum etch rate of 85 nm/min for MgO thin films was obtained at $Cl_2$(30%)/Ar(70%) gas mixing ratio. Also, the etch rate was measured by varying the etching parameters such as ICP rf power, dc-bias voltage, and chamber pressure. Plasma diagnostics was performed by Langmuir probe (LP) and optical emission spectroscopy (OES).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• 한국재료학회지
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• 제10권12호
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• pp.807-811
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• 2000

MFISFET (Metal-ferroelectric-nsulator-semiconductor-field effect transistor)에의 적용을 위해 CeO$_2$와 SrBi$_2$Ta$_2$O$_{9}$ 박막을 각각 r.f. sputtering 및 pulsed laser ablation법으로 제조하였다. CeO$_2$ 박막은 증착시 스퍼터링개스비 (Ar:O$_2$)에 따른 특성을 고찰하였다. Si(100) 기판 위에 $700^{\circ}C$에서 증착된 CeO$_2$ 박막들은 (200)방향으로 우선방향성을 가지고 성장하였고 $O_2$ 개스량이 증가함에 따라 박막의 우선방향성, 결정립도 및 표면거칠기는 감소하였다. C-V특성에서는 Ar:O$_2$가 1 : 1인 조건에서 제조된 박막이 가장 양호한 특성을 보였다. 제조된 박막들의 누설전류값은 100kV/cm의 전계에서 $10^{-7}$ ~$10^{-8}$ A의 차수를 보였다. CeO$_2$/Si 기판위에 성장된 SBT는 다결정질상의 치밀한 구조를 가지고 성장을 하였다 80$0^{\circ}C$에서 열처리된 SBT박막으로 구성된 MFIS구조의 C-V 특성에서 memory window 폭은 0.9V를 보였으며 5V에서 4$\times$$10^{-7}$ A/$\textrm{cm}^2$의 누설전류밀도를 보였다.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.64.1-64
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• 2003

A metal-ferroelectric [SrBi$_2$Ta$_2$O$\_$9/ (SBT)-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulator-semiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high of about 12 and a low leakage current density of less than 1${\times}$ 10e-8 A/$\textrm{cm}^2$ at 105 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and subface roughness of 3.2 nm. A capacitance-voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3V at a sweep voltage width of 12 V. The memory retention time was about 1 104s, comparable to the conventional Pt/SBT/SiO$\_$x/N$\_$y/(SiO$\_$N/)/Si. The gradual change of the capacitance indicates that some memory degradation mechanism is different from that in the Pt/SBT/SiON/Si structure.