• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.977-980
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• 1997

Ultraprecision machining process and MEMS technology have been taken more and more important position in machining of micro parts such as PDP and IT components, as the application field of micro parts increases. A micro machining center is very effective equipment for the fabrication of micro parts, because of its benefits such as lower power consumption, high precision and lower machining cost. Therefore, we study the possibility of application to the micro machining of barrier ribs used in PDP and also analyse the machining characteristics. The fabricated barrier rib has 30~$200\mu\textrm{m}$ pitch and was made by the flat endmill with the diameter of 0.2mm, 40, 000rpm condition.

• 한국정밀공학회지
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• 제28권2호
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• pp.245-250
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• 2011

A high-resolution shadow mask, a nanostencil, is widely used for high resolution lithography. This high-resolution shadowmask is often fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. In this study, FIB milling on 500-nm-thin SiN membrane was tested and characterized. 500 nm thick and $2{\times}2$ mm large membranes were made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 60 nm could be made into the membrane. The nanostencil could be used for nanoscale patterning by local deposition through the apertures.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.408-411
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• 2003

최근 활발하게 연구가 진행되고 있는 마이크로 인덕터는 자기 데이터 저장을 위한 헤드, 자기장 센서, 마이크로 변압기와 휴대폰의 수동 소자와 같은 다양한 분야에 이용되고 있다. 마이크로 인덕터를 제작하기 위해 UV-LIGA 공정을 개발하였다. 도금 공정을 이용하여 마이크로 인덕터의 철심과 구리선 제작하였다. 도금 공정을 위해 필요한 마이크로 몰드는 여러 종류의 thick photoresist를 이용하여 저응력 공정으로 제작하였다. 도금 공정을 이용하여 toroid형 마이크로 인덕터를 제작하였다. 도금 공정에서 발생 할 수 있는 응력을 최소화할 수 있는 공정을 개발하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.533-534
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• 2006

Micro pyramid pattern and its array are designed to enhance the brightness and its uniformity of LGP which is one of key parts in LCD. The designed micro pyramid patterns are fabricated on a Si-wafer first through MEMS process and then a Ni-stamper is electro-plated from the Si pattern master. Adopting the fabricated Ni-stamper, LGPs are injection molded at different mold temperatures and the fidelity of the pattern replication is estimated for each molding conditions and pattern locations. The replicated patterns are found to have some defect such as local short shot or micro weld line which are believed to have negative effect on the performance of the LGP.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 2003년도 제20회 춘계학술대회 논문집
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• pp.147-150
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• 2003

The purpose of this research was to develope components of micro solid propellant thruster. Micro solid propellant thruster had four basic components: combustion chamber, nozzle, solid propellant and micro heater for ignition. A performance of micro heater and characteristic of solid propellant was investigated. Micro heater was fabricated by conventional MEMS process and Platinum layer was used for heating element. Effect of geometry parameters on micro heater was tested. The temperature responses of heater with respect to each parameters was compared for a given electrical power. The characteristic of solid propellant(HTPB/AP) was investigated to obtain burning velocity in small chamber. Additionally, a capacity of filling propellant with high viscosity in small chamber was checked to guarantee for the micro fabrication.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1414-1415
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• 2006

Air-gap type film bulk acoustic wave resonator device using ZnO for piezoelectric layer and sacrifice layer, deposited by RF magnetron sputter with various conditions, fabricated in this study. Also, membrane$(SiO_2)$ and top and bottom electrode(both Al) of piezoelectric layer deposited by RF magnetron sputter. Using micro electro mechanical systems(MEMS) technique, sacrifice layer removed and then air-gap formed. The results of each process checked by XRD, AFM, SEM to obtain good quality device.

• Journal of Mechanical Science and Technology
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• 제20권12호
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• pp.2094-2104
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• 2006

As demands for complex microstructures with high aspect ratios have increased, the existing methods, MEMS and LIGA, have had difficulties coping with the number of masks and fabricable heights. A microstereolithography technology can meet these demands because it has no need of masks and is capable of fabricating high aspect ratio microstructures. In this technology, 3D part is fabricated by stacking layers, 2D sections, which are sliced from STL file, and the Dynamic Image Projection process enables the resin surface to be cured by a dynamic image generated with $DMD^{TM}$ (Digital Micromirror Device) and one irradiation. In this paper, we address optical design process for implementing this microstereolithography system that takes the light path based on DMD operation and image-formation on the resin surface using an optical design program into consideration. To verify the performance of this implemented microstereolithography system, complex 3D microstructures with high aspect ratios were fabricated.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.1175-1178
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• 2005

Brittle materials, especially single-crystal silicon wafer, are widely used for sensors, IC industry, and MEMS applications. e general machining process of crack easy materials is by chemical agents, but it is hazardous and time consuming. Also, it is difficult to get high aspect ratio micro structure. As an alternative tool, an AJM(Abrasive jet machining) is promising method in terms of high aspect ratio and production cost. In this study, to get more precise detail compared to general AJM, photo polymer mask, SU-8, used in photolithography was applied in AJM. Process parameters such as abrasive diameter, air pressure, nozzle diameter, flow rate of abrasive in AJM and a variety of conditions in spin coating were decided. Finally, micro channel and mixer was fabricated to see the efficiency of the AJM with photo polymer mask.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.892-895
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• 2003

This paper describes on RIE(Reactive Ion Etching) characteristics of 3C-SiC(Silicon Carbide) grown on Si(100) wafers. During RIE of 3C-SiC films in this work, $CHF_3$ gas is used to form of polymer as a side wall for excellent anisotropy etching. From this process, etch rates are obtained a $60{\sim}980{\AA}/min$ by various conditions such as $CHF_3$ gas flux, $O_2$ addition ratio, RF power and electrode distance. Also, approximately $40^{\circ}$ mesa structures are successfully formed at 100 mTorr $CHF_3$ gas flow ratio, 200 W RF power and 30 mm electrode distance. Moreover, vertical side wall is fabricated by anisotropy etching with 50% $O_2$ addition ratio and 25 mm electrode distance. Therefore, RIE of 3C-SiC films using $CHF_3$ could be applicable as fabrication process technology for high-temperature 3C-SiC MEMS applications.