• Journal of the Korean Society of Safety
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• v.33 no.1
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• pp.28-34
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• 2018

The purpose of this study is to fabricate a sensor module to detect the resistive leakage current (Igr) in real time that occurs to low voltage electric lines and to verify its reliability. In the case of the developed sensor module, wires are inserted into the zero current transformer (ZCT) and current transformer (CT) in advance and then the branch line is connected to the circuit breaker. The measurement result of the resistance of the distribution panel equipped with the developed sensor module shows that the resistance is $0.151m{\Omega}$ between the R and R phases, $0.169m{\Omega}$ between the S and S phases, and $0.178m{\Omega}$ between the T and T phases, respectively. The insulation resistance measured at AC 500 V and 1,000 V is $0.08m{\Omega}$ between the R, S, T and N phases, respectively. Then, the insulation resistance measured at DC 500 V is $83.3G{\Omega}$ between the R, S, T and G terminal, respectively. In addition, the applied withstanding voltage is AC 220 V/380 V/440 V and it was found that characteristics between all phases are good. This study measured the standby power by installing the developed sensor module at the rear of the MCCB and switching the circuit breaker on sequentially. The standby power is 1.350 W when one circuit breaker is turned on, 1.690 W when 2 circuit breakers are turned on, and 4.371 W when 10 circuit breakers are turned on. This study also verified the reliability of the standby power of the distribution panel equipped with the developed sensor module using the Minitab Program (Minitab PGM). Since the analysis shows the statistical average of 1.34627 in the reliable range of normal distribution, standard deviation of 0.001874, AD of 0.554, and P value of 0.140, it is found that the distribution panel equipped with the developed sensor module has high reliability.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.7
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• pp.6-13
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• 2006

Tin doped indium oxide(ITO) and Al doped zinc oxide(ZnO:Al) films, which are widely used as a transparent conductor in optoelectronic devices, were prepared by using the capacitively coupled DC magnetron sputtering method. ITO and ZnO:Al films with the optimum growth conditions showed each resistivity of $1.67{\times}10^{-3}[{\Omega}-cm],\;2.2{\times}10^{-3}[{\Omega}-cm]$ and transmittance of 89.61[%], 90.88[%] in the wavelength range of the visible spectrum. The two types of 5 inch-PDP cells with ZnO:Al and ITO transparent electrodes were made under the same manufacturing conditions. The PDP cell with ZnO:Al film was optimally operated in the mixing gas rate of Ne(base)-Xe(8[%]), and at gas pressure of 400[Torr]. It also shows the average measured brightness of $836[cd/m^2]$ at voltage range of $200{\sim}300$[V]. Luminous efficiency, one of the key parameter for high brightness and low power consumption, ranges from 1.2 to 1.6[lm/W] with increasing frequency of ac power supplier from 10 to 50[Khz]. The brightness and luminous efficiency are lower than those with ITO electrode by about 10[%]. However, these values are considered to be enough for the normal operation of PDP TV.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.4
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• pp.25-34
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• 2019

Recently, when a fault occurs at a long-distance point in a LVDC (low voltage direct current) distribution feeder in a light rail system, the magnitude of the current can decrease to less than that of the load current of a light rail system. Therefore, proper protection coordination method to distinguish a fault current from a load current is required. To overcome these problems, this paper proposes an optimal algorithm of protection devices for a LVDC distribution feeder in a light rail system. In other words, based on the characteristics of the fault current for ground resistance and fault location, this paper proposes an optimal operation algorithm of a selective relay to properly identify the fault current compared to the load current in a light rail system. In addition, this paper modelled the distribution system including AC/DC converter using a PSCAD/EMTDC S/W and from the simulation results for a real light rail system, the proposed algorithm was found to be a useful and practical tool to correctly identify the fault current and load current.