• Journal of Powder Materials
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• v.28 no.3
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• pp.233-238
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• 2021

Iron-based amorphous powder attracts increasing attention because of its excellent soft magnetic properties and low iron loss at high frequencies. The development of an insulating layer on the surface of the amorphous soft magnetic powder is important for minimizing the eddy current loss and enhancing the energy efficiency of high-frequency devices by further increasing the electrical resistivity of the cores. In this study, a hybrid insulating coating layer is investigated to compensate for the limitations of monolithic organic or inorganic coating layers. Fe₂O₃ nanoparticles are added to the flexible silicon-based epoxy layer to prevent magnetic dilution; in addition TiO₂ nanoparticles are added to enhance the mechanical durability of the coating layer. In the hybrid coating layer with optimal composition, the decrease in magnetic permeability and saturation magnetization is suppressed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.8
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• pp.461-465
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• 2016

n-type silicon shows the better tolerance towards metal impurities with a higher minority carrier lifetime compared to p-type silicon substrate. Due to better lifetime stability as compared to p-type during illumination made the photovoltaic community to switch toward n-type wafers for high efficiency silicon solar cells. We fabricated the front electrode of the n-type solar cell with AgAl paste. The electrodes characteristics of the AgAl paste depend on the contact junction depth that is closely related to the firing temperature. Metal contact depth with p+ emitter, with optimized depth is important as it influence the resistance. In this study, we optimize the firing condition for the effective formation of the metal depth by varying the firing condition. The firing was carried out at temperatures below $670^{\circ}C$ with low contact depth and high contact resistance. It was noted that the contact resistance was reduced with the increase of firing temperature. The contact resistance of $5.99m{\Omega}cm^2$ was shown for the optimum firing temperature of $865^{\circ}C$. Over $900^{\circ}C$, contact junction is bonded to the Si through the emitter, resulting the contact resistance to shunt. we obtained photovoltaic parameter such as fill factor of 76.68%, short-circuit current of $40.2mA/cm^2$, open-circuit voltage of 620 mV and convert efficiency of 19.11%.

• Journal of Korean Vacuum Science & Technology
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• v.4 no.3
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• pp.73-77
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• 2000

Single crystal and polycrystalline Si thin films were doped with phosphorus by a 2-zone diffusion method to develop the low-resistivity polycrystalline Si electrode for a hemispherical grain. Solid phosphorus source was used in order to achieve uniformly and highly doped surface region of polycrystalline Si films having rough surface morphology. In case of 2-zone diffusion method, it is proved that the heavy doping near the surface area can be achieved even at a relatively low temperature. SIMS analysis revealed that phosphorus doping concentration in case of using solid P as a doping source was about 50 times as that of phosphine source at 750$^{\circ}C$. Also, ASR analysis revealed that the carrier concentration was about 50 times as that of phosphine. In order to evaluate the electrical characteristics of doped polycrystalline Si films for semiconductor devices, MOS capacitors were fabricated to measure capacitance of polycrystalline Si films. In ${\pm}$2 V measuring condition, Si films, doped with solid source, have 8% higher $C_{min}$ than that of unadditional doped Si films and 3% higher $C_{min}$ than that of Si films doped with $PH_3$ source. The leakage current of these films was a few fA/${\mu}m^2$. As a result, a 2-zone diffusion method is suggested as an effective method to achieve highly doped polycrystalline Si films even at low temperature.

• Journal of the Korean Solar Energy Society
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• v.38 no.1
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• pp.45-55
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• 2018

Environmentally benign lead-free solder coated ribbon (e. g. SnCu, SnZn, SnBi${\cdots}$) has been intensively studied to interconnect cells without lead mixed ribbon (e. g. SnPb) in the crystalline silicon(c-Si) photovoltaic modules. However, high melting point (> $200^{\circ}C$) of non-lead based solder provokes increased thermo-mechanical stress during its soldering process, which causes early degradation of PV module with it. Hence, we proposed low-temperature conductive paste (CP) based tabbing method for lead-free ribbon. Modules, interconnected by the lead-free solder (SnCu) employing CP approach, exhibits similar output without increased resistivity losses at initial condition, in comparison with traditional high temperature soldering method. Moreover, 400 cycles (2,000 hour) of thermal cycle test reveals that the module integrated by CP approach withstands thermo-mechanical stress. Furthermore, this approach guarantees strong mechanical adhesion (peel strength of ~ 2 N) between cell and lead-free ribbons. Therefore, the CP based tabbing process for lead free ribbons enables to interconnect cells in c-Si PV module, without deteriorating its performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.412-412
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• 2009

Carbon-based nano materials have a significant effect on various fields such as physics, chemistry and material science. Therefore carbon nano materials have been investigated by many scientists and engineers. Especially, since graphene, 2-dimemsonal carbon nanostructure, was experimentally discovered graphene has been tremendously attracted by both theoretical and experimental groups due to their extraordinary electrical, chemical and mechanical properties. Electrical conductivity of graphene is about ten times to that of silicon-based material and independent of temperature. At the same time silicon-based semiconductors encountered to limitation in size reduction, graphene is a strong candidate substituting for silicon-based semiconductor. But there are many limitations on fabricating large-scale graphene sheets (GS) without any defect and controlling chirality of edges. Many scientists applied micromechanical cleavage method from graphite and a SiC decomposition method to the fabrication of GS. However these methods are on the basic stage and have many drawbacks. Thereupon, our group fabricated GS through Thermo-electrical Pulse Induced Evaporation (TPIE) motivated by arc-discharge and field ion microscopy. This method is based on interaction of electrical pulse evaporation and thermal evaporation and is useful to produce not only graphene but also various carbon-based nanostructures with feeble pulse and at low temperature. On fabricating GS procedure, we could recognize distinguishable conditions (electrical pulse, temperature, etc.) to form a variety of carbon nanostructures. In this presentation, we will show the structural properties of OS by synthesized TPIE. Transmission Electron Microscopy (TEM) and Optical Microscopy (OM) observations were performed to view structural characteristics such as crystallinity. Moreover, we confirmed number of layers of GS by Atomic Force Microscopy (AFM) and Raman spectroscopy. Also, we used a probe station, in order to measure the electrical properties such as sheet resistance, resistivity, mobility of OS. We believe our method (TPIE) is a powerful bottom-up approach to synthesize and modify carbon-based nanostructures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.151-151
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• 2009

Recently, there has been increasing interest in amorphous oxide semiconductors to find alternative materials for an amorphous silicon or organic semiconductor layer as a channel in thin film transistors(TFTs) for transparent electronic devices owing to their high mobility and low photo-sensitivity. The fabriction of amorphous oxide-based TFTs at room temperature on plastic substrates is a key technology to realize transparent flexible electronics. Amorphous oxides allows for controllable conductivity, which permits it to be used both as a transparent semiconductor or conductor, and so to be used both as active and source/drain layers in TFTs. One of the materials that is being responsible for this revolution in the electronics is indium-zinc-tin oxide(IZTO). Since this is relatively new material, it is important to study the properties of room-temperature deposited IZTO thin films and exploration in a possible integration of the material in flexible TFT devices. In this research, we deposited IZTO thin films on polyethylene naphthalate substrate at room temperature by using magnetron sputtering system and investigated their properties. Furthermore, we revealed the fabrication and characteristics of top-gate-type transparent TFTs with IZTO layers, seen in Fig. 1. The experimental results show that by varying the oxygen flow rate during deposition, it can be prepared the IZTO thin films of two-types; One a conductive film that exhibits a resistivity of $2\times10^{-4}$ ohm${\cdot}$cm; the other, semiconductor film with a resistivity of 9 ohm${\cdot}$cm. The TFT devices with IZTO layers are optically transparent in visible region and operate in enhancement mode. The threshold voltage, field effect mobility, on-off current ratio, and sub-threshold slope of the TFT are -0.5 V, $7.2\;cm^2/Vs$, $\sim10^7$ and 0.2 V/decade, respectively. These results will contribute to applications of select TFT to transparent flexible electronics.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1254_1255
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• 2009

The composites were fabricated by adding 30, 35, 40, 45[vol.%] Zirconium Diboride(hereafter, $ZrB_2$) powders as a second phase to Silicon Carbide(hereafter, SiC) matrix. The physical, mechanical and electrical properties of electroconductive SiC ceramic composites by Spark Plasma Sintering(hereafter, SPS) were examined. Reactions between $\beta$-SiC and $ZrB_2$ were not observed in the XRD analysis. The relative density of SiC+30[vol.%]$ZrB_2$, SiC+35[vol.%]$ZrB_2$, SiC+40[vol.%]$ZrB_2$ and SiC+45[vol.%]$ZrB_2$ composites are 88.64[%], 76.80[%], 79.09[%] and 88.12[%], respectively. The XRD phase analysis of the electroconductive SiC ceramic composites reveals high of SiC and $ZrB_2$ and low of $ZrO_2$ phase. The electrical resistivity of SiC+30[vol.%]$ZrB_2$, SiC+35[vol.%]$ZrB_2$, SiC+40[vol.%]$ZrB_2$ and SiC+45[vol.%]$ZrB_2$ composites are $6.74{\times}10^{-4}$, $4.56{\times}10^{-3}$, $1.92{\times}10^{-3}$ and $4.95{\times}10^{-3}[{\Omega}{\cdot}cm]$ at room temperature, respectively. The electrical resistivity of SiC+30[vol.%]$ZrB_2$, SiC+35[vol.%]$ZrB_2$, SiC+40[vol.%]$ZrB_2$ and SiC+45[vol.%]$ZrB_2$ are Positive Temperature Coefficient Resistance(hereafter, PTCR) in temperature ranges from 25[$^{\circ}C$] to 500[$^{\circ}C$]. It is convinced that SiC+40[vol.%]$ZrB_2$ composite by SPS can be applied for heater or electrode.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.475-480
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• 2017

In this paper, the conductivity of the fine pattern is improved in the insulating substrate by laser-induced forward transfer (LIFT) process. The high laser beam energy generated in conventional laser induced deposition processes induces problems such as low deposition density and oxidation of micro-patterns. These problems were improved by using a polymer coating layer for improved deposition accuracy and conductivity. Chromium and copper were used to deposit micro-patterns on silicon wafers. A multi-pulse laser beam was irradiated on a metal thin film to form a seed layer on an insulating substrate(SiO2) and electroless plating was applied on the seed layer to form a micro-pattern and structure. Irradiating the laser beam with multiple scanning method revealed that the energy of the laser beam improved the deposition density and the surface quality of the deposition layer and that the electric conductivity can be used as the microelectrode pattern. Measuring the resistivity after depositing the microelectrode by using the laser direct drawing method and electroless plating indicated that the resistivity of the microelectrode pattern was $6.4{\Omega}$, the resistance after plating was $2.6{\Omega}$, and the surface texture of the microelectrode pattern was uniformly deposited. Because the surface texture was uniform and densely deposited, the electrical conductivity was improved about three fold.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.9
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• pp.1757-1763
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• 2009

The composites were fabricated by adding 0, 15, 20, 25[vol.%] Zirconium Diboride(hereafter, $ZrB_2$) powders as a second phase to Silicon Carbide(hereafter, SiC) matrix. The physical, mechanical and electrical properties of electroconductive SiC ceramic composites by Spark Plasma Sintering(hereafter, SPS) were examined. Reactions between ${\beta}-SiC$ and $ZrB_2$ were not observed in the XRD analysis. The relative density of mono SiC, SiC+15[vol.%]$ZrB_2$, SiC+20[vol.%]$ZrB_2$ and SiC+25[vol.%]$ZrB_2$ composites are 90.93[%], 74.62[%], 74.99[%] and 72.61[%], respectively. The XRD phase analysis of the electroconductive SiC ceramic composites reveals high of SiC and $ZrB_2$ and low of $ZrO_2$ phase. The lowest flexural strength, 108.79[MPa], shown in SiC+15[vol.%] $ZrB_2$ composite and the highest - 220.15[MPa] - in SiC+20[vol.%] $ZrB_2$composite at room temperature. The trend of the mechanical properties of the electroconductive SiC ceramic composites moves in accord with that of the relative density. The electrical resistivities of mono SiC, SiC+15[vol.%]$ZrB_2$, SiC+20[vol.%]$ZrB_2$ and SiC+25[vol.%]$ZrB_2$ composites are 4.57${\times}10^{-1}$, 2.13${\times}10^{-1}$, 1.53${\times}10^{-1}$ and 6.37${\times}10^{-2}$[${\Omega}$ cm] at room temperature, respectively. The electrical resistivity of mono SiC, SiC+15[vol.%]$ZrB_2$. SiC+20[vol.%]$ZrB_2$ and SiC+25[vol.%]$ZrB_2$ are Negative Temperature Coefficient Resistance(hereafter, NTCR) in temperature ranges from 25[$^{\circ}C$] to 100[$^{\circ}C$]. The declination of V-I characteristics of SiC+20[vol.%]$ZrB_2$ composite is 3.72${\times}10^{-1}$. It is convinced that SiC+20[vol.%]$ZrB_2$ composite by SPS can be applied for heater or electrode above 1000[$^{\circ}C$]