• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.1
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• pp.50-55
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• 2012

This paper proposes an optima] many-core processor architecture that meets the requirements of low power and high performance for different ultrasonic image resolutions in hand-held ultrasonic devices. To identify the optimal many-core architecture, seven different PE configurations are simulated for processing ultrasonic images in terms of execution performance and energy consumption. Experimental results indicate that the highest energy efficiencies are achieved at PEs=1,024, 64, and 256 for ultrasonic images at $256{\times}256$, $320{\times}240$, and $800{\times}480$ resolutions, respectively. In addition, the maximum area efficiencies are obtained at PEs=256 (for $256{\times}256$ and $800{\times}480$ image resolutions) and 64 (for $320{\times}240$ image resolution).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.9-16
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• 2009

Energy consumption as well as performance should be considered when designing up-to-date multicore processors. In this paper, we propose new design technique to reduce the energy consumption in the instruction cache for multicore processors by using modified filter cache. The filter cache has been recognized as one of the most energy-efficient design techniques for singlecore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential to reduce the energy consumption in a multicore processor. The proposed technique reduces the energy consumption in the instruction cache for multicore processors by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed architecture reduces the energy consumption in the instruction cache for multicore processors by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture.

• Journal of the Korean Solar Energy Society
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• v.32 no.6
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• pp.106-112
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• 2012

As a fuel cell converts the chemical energy of the fuel cell into electrical energy by electrochemical reaction, the fuel cell system is uniquely integrated technique including fuel processor, fuel cell stack, power conditioning system. The residential fuel cell-PCS(Power Conditioning System) needs to convert efficiently the DC current produced by the fuel cell into AC current using single-phase DC-AC inverter. A single-phase DC-AC inverter has naturally low frequency ripple which is twice frequency of the output current. This low frequency(120Hz) ripple reduces the efficiency of the fuel cell. This paper presents notch filter with IP voltage controller to reject specific 120Hz current ripple in single-phase inverter. The notch filter is designed that suppress just only specific frequency component and no phase delay. Finally, the proposed notch filter design method has been verified with computer simulation and experimentation.

• Journal of Digital Convergence
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• v.13 no.8
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• pp.245-251
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• 2015

If a digital signage system is operated in PC mounted in the Window OS then the implementing price is very high. For resolving this problem, we used the Smartphone mounted in ARM Cortex family of multi-core processor-based mobile platform. We developed a low-power low-cost digital signage system and a remote convergence content management program based on web server. This convergence system manages advertising content to a remote control device anywhere using remote control technology. This system is one integrated system with display and is a low-power consumed and is developed in very efficient hardware interface. And condition sensors(intensity of illumination, temperature, weather, GPS etc) is equipped in the developed system. Automatic contents builder and Context-aware SMIL module is also implemented in the convergence system. We achieved over 50% power savings comparing with conventional Window OS system and 16 points multi-touch in our system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.440-447
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• 2002

This paper considerated about exact flow volume calculation method from factors having an influence on measurement and introduced in anesthesia ventilator realized spirometry system. System used differential pressure sensing method with factors, that is temperature, pressure, gas density, humidity and mucus etc. System optimized for low power system for mobile system. System composed analog interface part, signal processing part, display part. Analog interface part have differential pressure flow sensor and defferential pressure sensor. Signal processing part have AVR processor for low power system display part use serial port (RS232, SPT). so it display at pc monitor or send to anesthesia ventilator. System is stable by linearizing 2th characteristics of flow-differential pressure, auto correction of sensor. Noise reduced by algorithm with analog filter and digital processing. Small, light, low power system is good at mobile system and applied to patient in emergency or mobile. and, System is useful at anesthesia ventilator by using flow sensor.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.241-251
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• 2007

Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by $37%{\sim}60%$ compared to the traditional direct-mapped instruction cache.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.143-150
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• 2005

This paper proposes a new $radix-2^4$ FFT algorithm and an efficient pipeline architecture based on this new algorithm for OFDM systems. The pipeline architecture based on the new algorithm has the same number of multipliers as that of the $radix-2^2$ algorithm. However, the multiplier complexity could be reduced by more than $30\%$ by replacing one half of the programmable complex multipliers by the newly proposed CSD constant complex multipliers. From synthesis simulations of a standard 0.35um CMOS Samsung process, a proposed CSD constant complex multiplier achieved more than $60\%$ area efficiency when compared with the conventional programmable complex multiplier. This promoted efficiency can be used for the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.