• The Journal of Engineering Geology
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• v.3 no.2
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• pp.167-176
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• 1993

The high resolution studies for shallow seismic reflection are carried out using 24-channel seismograph and the high sensitivity geophone(50-500Hz). In order to study the underground structures such as small faults, fractures, cracks and cavities, it is of great importance to enhance high resolution of the seisrnic records for the targets vertically and laterally. In analysis of high resolution seismic reflection, Nyquist frequency($F_N$) should be lager than the highest frequency in the records and the highest wave number should not be exceed the Nyquist wave number($1/2{\Delta}x$). The highest frequency above the Nyquist will be removed using low pass filter or antialias filter. The trace interval Ax should be taken into account so that the highest wave number(f/v) can be less than $1/2{\Delta}x$. The Fraunhofer diffraction of a hyperbola seismic section above the tunnel appeares on the common offset method, and little first arrivals of direct wave on the single-end shooting, delayed strong impulsive reflections are also shown above the tunnel. Ray Method(Cherveney and Psencik, 1983) also represents the same results that the reflected waves from the tunnel are delayed and single impulsive with little first arrivals, while transrnitted waves through the tunnel are delayed with low frequency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12A
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• pp.1153-1160
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• 2005

OFDM/OQAM(Offset QAM)-IOTA system requires the IOTA(Isotropic Orthogonal Transform Algorithm) function that has superior localization property in time and frequency domain instead of guard interval used for conventional OFDM/QAM system to be robust to multipath channel. Therefore, OFDM/OQAM-IOTA system has more spectral efficiency than conventional OFDM/QAM system. But, when channel estimation scheme for conventional OFDM/QAM system is applied straightforwardly to OFDM/OQAM-IOTA system, an intrinsic Inter- symbol-Interference is observed. So suitable preamble structure for the channel estimation scheme of OFDM/OQAM-IOTA system is required. In this paper, we propose a new preamble structure that is appropriate to OPDM/OQAM-IOTA system and then perform ideal channel estimation and practical channel estimation in low-to-medium mobile speed and compare them with conventional OFDM/QAM system. Simulation results show that OFDM/OQAM-IOTA system with proposed preamble structure has 1.5 dB Eb/NO gain on Target BER $10^{-3}$ and about $25\%$ transmission rate gain against the conventional OFDM/QAM system considering quarter of FFT size as guard interval size.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.335-338
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• 2004

We suggest Q-band MEMS MIMIC (Millimeter wave Monolithic Integrated Circuit) HEMT Oscillator using DAML (Dielectric-supported Airgapped Mcrostrip Line) structure. We elevated the signal lines from the substrate using dielectric post, in order to reduce the substrate dielectric loss and obtain low losses at millimeter-wave frequency. These DAML are composed with heist of $10\;{\mu}m$ and post size with $20\;{\mu}m\;{\times}\;20\;{\mu}m$. The MEMS oscillator was successfully integrated by the process of $0.1\;{\mu}m$ GaAs PHEMTs, CPW transmission line and DAML. The phase noise characteristic of the MEMS oscillator was improved more than 7.5 dBc/Hz at a 1 MHz offset frequency than that of the CPW oscillator And the high output power of 7.5 dBm was measured at 34.4 GHz.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.476-482
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• 2014

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. IEEE 802.15.4 LR-WPAN system using 2.45 GHz frequency band is very popular for the sensor applications. However, since LR-WPAN only supports the data rate of 250 kbps, it has a limit to be applied to various sensor networks. Therefore, we define the preamble structure which can support the data rates of 31.25 kbps, 62.5 kbps, 125 kbps, and present the low-complexity hardware architecture for time synchronizer based on double-correlation algorithm which can resist the CFO (carrier frequency offset). Implementation results show that the proposed time synchronizer include the logic slice of 18.36 K and four DSP48s, which are reduced at the rate of 79.1% and 99.4%, respectively, compared with existing architecture.

• Journal of IKEEE
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• v.18 no.1
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• pp.119-127
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• 2014

This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.7
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• pp.372-379
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• 2014

When a hand-held device with limited battery transmits and receives data using short-range wireless communication systems, such as WLAN(Wireless Local Area Network) or high speed WPAN(Wireless Personal Area Network), instead of mobile communication systems, the device is able to reduce the power consumption due to the reduced transmission distance. However, if there are many WLAN or high speed WPAN systems around the device, non-negligible power may be consumed by receiving and decoding the packets which have nothing to do with the device. In this paper, we propose a scheme reducing the power consumption by including physical-layer ID in WLAN or WPAN packets and avoiding unnecessary packet receptions. Also, we describe a method to determine the optimum number of physical-layer IDs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.9
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• pp.820-825
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• 2004

In this paper an octave tuning voltage controlled oscillator which is used in set-top TV tuner was designed. Oscillation frequency range is 0.9 GHz～2.2 GHz with 1.3 GHz bandwidth. By using 4 varactor diodes in base and emitter of transistor, wide-band tuning, sweep linearity and low phase noise could be achieved. Designed VCO requires a tuning voltage of 0 V ～ 20 V and DC consumption of 10 V and 15 mA. Designed VCO exhibits an output power of 5.3 dBm $\pm$1.1 dB and a phase noise below -94.8 dBc/Hz ＠ 10 kHz over the entire frequency range. The sweep linearity shows 65 MHz/V with a deviation of $\pm$10 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.398-402
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• 2003

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator) applied to FMCW(Frequency Modulated Continuous Wave)Radar as stable source is implemented and constructed with a MESFET for low noise, a dielectric resonator of high frequency selectivity, and high Q varator diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated thrash harmonic balance simulation technique to provide the optimum performance. The measured result of a fabricated VCDRO shows that output is 2.22dBm at 12.05GHz, harmonic suppression -30dBc, phase noise -130dBc at 100kHz offset, and sweep range of varator diode $\pm$18.7MHz, respectively. This oscillator will be available to FMCW Radar.