• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.67-71
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• 2012

In this paper, a push-push oscillator at K-band with a double H-shape metamaterial resonator (DHMR) based on high-Q is proposed with metamaterial structure to improve the phase noise and output power. The proposed oscillator shows low phase noise and high output power. DHMR is designed to be high-Q at resonance frequency through strong coupling of E-field. oscillators which are combined in push-push structure improve output power. The propose push-push oscillator shows the output power of 3.1 dBm, the fundamental signal suppression of -23.7 dBc and phase noise of -116.28 dBc at 100 kHz offset frequency and 20.20 GHz center frequency.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.342-347
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• 2017

We present a precision instrument amplifier (IA) designed for bio-potential acquisition. The proposed IA employs a capacitively coupled instrument amplifier (CCIA) structure to achieve a rail-to-rail input common-mode range and low gain error. A positive feedback loop is applied to boost the input impedance. Also, DC servo loop (DSL) with pseudo resistors is adopted to suppress electrode offset for bio-potential sensing. The proposed amplifier was designed in a $0.18{\mu}m$ CMOS technology with 1.8V supply voltage. Simulation results show the integrated noise of $1.276{\mu}Vrms$ in a frequency range from 0.01 Hz to 1 KHz, 65dB SNR, 118dB CMRR, and $58M{\Omega}$ input impedance respectively. The total current of IA is $38{\mu}A$. It occupies $740{\mu}m$ by $1300{\mu}m$ including the passive on-chip low pass filter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.180-185
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• 2000

In this paper, we designed 2303.15MHz Sequency synthesizer for the purpose of the phase noise prediction. For the modeling of phase noise Oersted in the designed system through inooducing the noise-modeling method suggested by Lascari we analyzied a variation of phase noise as according as that of offest frequency. Especially, for the third-order system of the PLL among some kinds of phase noise generated from VCO we analyzed the aspect of 1/f-noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically 1/f-noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor has made an ease of the access of the 1/f-noise variance. we showed a numerical formula of 1/f-noise variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2001.11b
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• pp.676-681
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• 2001

We usually divide the noise of exhaust system into pulsation noise and flow noise. Pulsation noise is the shock wave to occur when the burning gas of low pressure emits and include harmonic having basic frequency as the exhaust cycle of engine. Flow noise is the noise that is produced when gas flow emits into the atmosphere through the pipe and has the character of frequency like pink noise which has the high level of high frequency component. A muffler is divided into reflective type and absorptive type. We usually use the muffler compounding the property of them. In this study, it is the case of transfer matrix method that a muffler is compounded to analyze the elements of each section according to sound wave's proceed direction. But we use simple model. So, we use finite element method that takes short time to analyze. Acoustic analysis gives us transfer matrix to use FEA of SYSNOISE and we use STAR-CD for fluid analysis. We made database that is based on analytical results about the muffler of expansion type, extended type, offset type, reverse type, and perforated type and developed the muffler design system to perform work efficiently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.282-290
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• 2006

In this paper, we propose an enhanced Timing Estimator algorithm for 2.45GHz LR-WPAN receiver. Because an expensive and highly efficient oscillator can't be used for low-cost implementation, a Timing Estimator algorithm having stable operation in the channel environment with center frequency tolerance of 80 ppm is required. To enhance the robustness to frequency offset and the stability of receiver performance, multiple delay differential filter is adopted. By utilizing the characteristic that the correlation result between the output signal of Multiple delay differential filter and reference signal is restricted on the In-phase part of the correlator output, a coherent detection scheme instead of the typical noncoherent one is adopted for Timing Estimator. The application of the coherent detection scheme is suitable for LR-WPAN receiver aimed at low-cost, low-power, and low-complexity, since it can remove performance degradation due to squaring loss of I/Q squaring operation and decrease implementation complexity. Computer simulation results show that the proposed algorithm achieved performance improvement compared with the differential detection-based noncoherent scheme by 2dB in average.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.73-79
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• 2020

Modern radar system requires high spectral purity and low phase noise characteristics for very low RCS target detection and high resolution SAR (Synthetic Aperture Radar) image. This paper presents a new X-band high stable frequency synthesizer for high performance radar system, which combines DAS (Direct Analog Synthesizer) and DDS (Direct Digital Synthesizer) techniques, in order to cope with very low phase noise and high frequency agility requirements. This synthesizer offers more than 10% operating bandwidth in X-band frequency and fast agile time lower than 1 usec. Also, the phase noise at 10kHz offset is lower than -136dBc/Hz, which shows an improvement of more than 10dB compared to the current state of art frequency synthesizer. This architecture can be applied to L-band and C-band application as well. This frequency synthesizer is able to used in modern AESA (Active Electronically Scanned Array) radar system and high resolution SAR application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2480-2486
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• 2012

The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.205-209
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• 2000

Modem wireless communication equipments provides various multimedia and aims at the development of low-power, minimum size and weight, and low-cost implimentations. Because of the heterodyne architecture which was invented many decades ago in the wireless communication system using too many components, it was difficult to make it small, compact and On-Chip so it does not proper for future communication. That gives rise a new developing architecture, so called, Direct Conversion. Because The Direct Conversion down-converts the wireless frequency band to baseband directly, it does not need using additive components and has a merit of reduction in power dissipation. We describes the Direct Conversion architecture and DC-Offset, which must be solved, theorectically and predicts system performance enhancement when adopt the AC-Coupling method.