• Journal of Computing Science and Engineering
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• 제6권4호
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• pp.310-319
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• 2012

Next generation wireless receivers demand low computational complexity algorithms with high computing power in order to perform fast signal detections and error estimations. Several signal detection and estimation algorithms have been proposed for next generation wireless receivers which are primarily designed to provide reasonable performance in terms of signal to noise ratio (SNR) and bit error rate (BER). However, none of them have been chosen for direct implementation as they offer high computational complexity with relatively lower computing power. This paper presents a low-complexity power-efficient algorithm that improves the computing power and provides relatively faster signal detection for next generation wireless multiuser receivers. Measurement results of the proposed algorithm are provided and the overall system performance is indicated by BER and the computational complexity. Finally, in order to verify the low-complexity of the proposed algorithm we also present a formal mathematical proof.

• Journal of Positioning, Navigation, and Timing
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• 제11권2호
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• pp.91-98
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• 2022

In the next generation wireless communication system, the beamforming technique based on a massive antenna is one of core technologies for transmitting and receiving huge amounts of data, efficiently and accurately. For highly performed and highly reliable beamforming, it is required to accurately estimate the Angle of Arrival (AOA) for the desired signal incident to an antenna. Employing the massive antenna with a large number of elements, although the accuracy of the AOA estimation is enhanced, its computational complexity is dramatically increased so much that real-time communication is difficult. In order to improve this problem, AOA estimation algorithms based on the massive antenna with the low computational complexity have been actively studied. In this paper, we compute and analyze the computational complexity of the cascade AOA estimation algorithm based on the Flexible Massive Concentric Circular Array (FMCCA). In addition, its computational complexity is compared to conventional AOA estimation techniques such as the Multiple Signal Classification (MUSIC) algorithm with the high resolution and the Only Beamspace MUSIC (OBM) algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.298-300
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• 2004

In the decoding process of interframe wavelet coding, the inverse wavelet transform requires huge computational complexity. However, the decoder may need to be used in various devices such as PDAs, notebooks, PCs or set-top Boxes. Therefore, the decoder's complexity should be adapted to the processor's computational power. A decoder designed in accordance with the processor's computational power would provide optimal services for such devices. So, it is natural that the complexity scalability and the low complexity codec are also listed in the requirements for scalable video coding. In this contribution, we develop a method of controlling and lowering the complexity of the spatial wavelet transform while sustaining almost the same coding efficiency as the conventional spatial wavelet transform. In addition, the proposed method may alleviate the ringing effect for certain video data.

• Journal of Electrical Engineering and Technology
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• 제11권4호
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• pp.1020-1026
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• 2016

Motion estimation (ME) algorithms supporting quarter-pixel accuracy have been recently introduced to retain detailed motion information for high quality of video in the state-of-the-art video compression standard of H.264/AVC. Conventional sub-pixel ME algorithms in the spatial domain are faced with a common problem of computational complexity because of embedded interpolation schemes. This paper proposes a low-complexity sub-pixel motion estimation algorithm in the transform domain utilizing shifting matrix. Simulations are performed to compare the performances of spatial-domain ME algorithms and transform-domain ME algorithms in terms of peak signal-to-noise ratio (PSNR) and the number of bits per frame. Simulation results confirm that the transform-domain approach not only improves the video quality and the compression efficiency, but also remarkably alleviates the computational complexity, compared to the spatial-domain approach.

• 한국전자파학회논문지
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• 제22권7호
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• pp.705-710
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• 2011

본 논문에서는 Chase 알고리즘 기반의 연판정 e-BCH 복호시 계산량을 감소하는 알고리즘을 제시하였다. Chase 알고리즘 기반의 연판정 e-BCH 복호 방식은 test pattern을 만들기 위해 수신 데이터 중 신뢰성이 낮은 데이터를 순서대로 찾기 위해 ordering을 한다. 데이터를 ordering하는 과정과 test pattern 수 만큼을 수신 데이터와 비교함으로써 최적의 복호 열을 찾는 과정에서 높은 복잡도가 요구되며, 본 논문에서는 이러한 복잡도를 줄이는 방안을 제시하여 계산량 및 성능 관점에서 비교 분석하였다.

• 한국통신학회논문지
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• 제31권4C호
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• pp.303-309
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• 2006

By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

• ETRI Journal
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• 제27권5호
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• pp.639-642
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• 2005

This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

• ETRI Journal
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• 제40권2호
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• pp.218-226
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• 2018

Multiuser detection (MUD) and channel estimation techniques in space-division multiple-access aided orthogonal frequency-division multiplexing systems recently has received intensive interest in receiver design technologies. The maximum likelihood (ML) MUD that provides optimal performance has the cost of a dramatically increased computational complexity. The minimum mean-squared error (MMSE) MUD exhibits poor performance, although it achieves lower computational complexity. With almost the same complexity, an MMSE with successive interference cancellation (SIC) scheme achieves a better bit error rate performance than a linear MMSE multiuser detector. In this paper, hybrid ML-MMSE with SIC adaptive multiuser detection based on the joint channel estimation method is suggested for signal detection. The simulation results show that the proposed method achieves good performance close to the optimal ML performance at low SNR values and a low computational complexity at high SNR values.

• Journal of Information Processing Systems
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• 제2권3호
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• pp.153-158
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• 2006

In this paper, we propose an image interpolator for low computational complexity. The proposed image interpolator supports the image scaling using a modified cubic convolution interpolation between the input and output resolutions for a full screen display. In order to reduce the computational complexity, we use the difference in value of the adjacent pixels for selecting interpolation methods and linear function of the cubic convolution. The proposed image interpolator is compared with the conventional one for the computational complexity and image quality. The proposed image interpolator has been designed and verified by Verilog HDL(Hardware Description Language). It has been synthesized using the Xilinx VirtexE FPGA, and implemented using an FPGA-based prototype board.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1259-1262
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• 2006

In this paper, we propose a modified cubic convolution interpolation for the enlargement or reduction of digital images using a pixel difference value. The proposed method has a low complexity: the number of multiplier of weighted value to calculate one pixel of a scaled image has seven less than that of cubic convolution interpolation has sixteen. We use the linear function of the cubic convolution and the difference pixel value for selecting interpolation methods. The proposed method is compared with the conventional one for the computational complexity and the image quality. The simulation results show that the proposed method has less computational complexity than one of the cubic convolution interpolation.