• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.9-10
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• 2000

The wide viewing angle and fast response time characteristics of negative dielectric anisotropy nematic liquid crystal (NLC) using a novel vertical-alignment (VA) - 1/4 ${\pi}$ cell mode on a homeotropic alignment layer were investigated. Good voltage-transmittance curves and low driving voltage using the novel VA - 1/4 ${\pi}$ cell mode without a negative compensation film were obtained. The iso-viewing angle characteristics of NLC using the novel VA - 1/4 ${\pi}$ cell mode without a negative compensation film can be achieved. The fast response time of 24.4 ms in NLC was successfully measured. The iso-viewing angle, fast response time, and low driving voltage characteristics using the novel VA - 1/4 ${\pi}$ cell mode can be achieved.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.4
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• pp.332-336
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• 2000

We have developed a novel vertical-alignment(VA) -$\pi$ cell mode that provides a wide viewing angle and fast response times for nematic liquid crystal(NLC) with negative dielectric anisotropy on a homeotropic polymide(PI) surfaces. Good voltage-transmittance curves and low driving voltages were achieved with the new VA-$\pi$ cell mode without a negative compensation film. Iso-viewing angle characteristics using the new VA-$\pi$ cell mode without a negative compensation film was also successfully observed. As well a fast response time of 31.7 ms for a new VA-$\pi$ mode was measured. Consequently the iso-viewing angel fast response time and low driving voltage characteristics using a VA-$\pi$ cell can be achieved.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.4
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• pp.151-157
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• 2023

RPL (IPv6 Routing Protocol for Low-power Lossy Network) is a standardized routing protocol for LLNs (Low power and Lossy Networks) by the IETF (Internet Engineering Task Force). RPL creates routes and builds a DODAG (Destination Oriented Directed Acyclic Graph) through OF (Objective Function) defining routing metrics and optimization objectives. RPL supports a leaf mode which does not allow any child nodes. In this paper, we propose INFRA-RPL which provides a dynamic leaf mode functionality to a leaf node with the mobility. The proposed protocol is implemented in the open-source IoT operating system, Contiki-NG and Cooja simulator, and its performance is evaluated. The evaluation results show that INFRA-RPL outperforms the existing protocols in the terms of PDR, latency, and control message overhead.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.445-453
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• 2015

A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a $0.18-{\mu}m$ CMOS process occupies an area of $750{\mu}m{\times}610{\mu}m$. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes $3{\mu}A$ under normal operating conditions and $0.45{\mu}A$ under standby mode.

• The KIPS Transactions:PartA
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• v.15A no.2
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• pp.69-74
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• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2012.05a
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• pp.86-90
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• 2012

In this paper, the combustion instabilities which may occur in the hybrid rocket were studied. The rocket combustor where the vortexes can be generated was designed, and the experiments were performed. The investigations about characteristics on the presence of the diaphragm, the length of the fuel, the diameter of the fuel port, the diameter of the diaphragm, the diameter of the nozzle throat, and the variation of the Ox massflow rate were conducted. The main resonant frequency of the combustion pressure is regarded by the Vortex shedding mode, and it is considered that the other resonant frequency of the pressure fluctuation is hybrid low frequency, or helmholtz mode.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2012.10a
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• pp.388-393
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• 2012

Vibration condition monitoring at low rotational speeds is still a challenge. Acoustic emission (AE) is the most used technique when dealing with low speed bearings. At low rotational speeds, the energy induced from surface contact between raceway and rolling elements is very weak and sometimes buried by interference frequencies. This kind of issue is difficult to solve using vibration monitoring. Therefore some researchers utilize artificial damage on inner race or outer race to simplify the case. This paper presents vibration signal analysis of low speed slewing bearings running at a low rotational speed of 15 rpm. The natural damage data from industrial practice is used. The fault frequencies of bearings are difficult to identify using a power spectrum. Therefore the relatively improved method of empirical mode decomposition (EMD), ensemble EMD (EEMD) is employed. The result is can detect the fault frequencies when the FFT fail to do it.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).