• Title/Summary/Keyword: Lot Array

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Parallel Processing for Integral Imaging Pickup Using Multiple Threads

  • Jang, Young-Hee;Park, Chan;Park, Jae-Hyeung;Kim, Nam;Yoo, Kwan-Hee
    • International Journal of Contents
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    • v.5 no.4
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    • pp.30-34
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    • 2009
  • Many studies have been done on the integral imaging pickup whose objective is to get efficiently elemental images from a lens array with respect to three-dimensional (3D) objects. In the integral imaging pickup process, it is necessary to render an elemental image from each elemental lens in a lens array for 3D objects, and then to combine them into one total image. The multiple viewpoint rendering (MVR) is one of various methods for integral imaging pickup. This method, however, has the computing and rendering time problem for obtaining element images from a lot of elemental lens. In order to solve the problems, in this paper, we propose a parallel MVR (PMVR) method to generate elemental images in a parallel through distribution of elemental lenses into multiple threads simultaneously. As a result, the computation time of integral imaging using PMVR is reduced significantly rather than a sequential approach and then we showed that the PMVR is very useful.

Performance Analysis for Beamformer of Adaptive Array Antenna in W-CDMA Communication System (W-CDMA 통신 시스템에서 적응배열안테나의 Beamformer 성능분석)

  • 이정길;홍상완;이병섭
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.6B
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    • pp.1127-1135
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    • 2000
  • The beamforming procedure in Adaptive Array Antenna System is affected by signal degradation and data rate due to DS-CDMA characteristics. Until this time, a lot of techniques are suggested to overcome this problems. This paper shows the simulation result about the beamforming performance of symbol level system that process slow data rate, compensated signal by despreading procedure in front of beamformer, and that of chip level system that process chip level signal without it. we analysis the performance using MSE, beam pattern, scattering points of beamformer output. chip level system is superior to symbol level system in time varying channel, while the performance of them didn't have difference in static channel.

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PARAFAC Tensor Reconstruction for Recommender System based on Apache Spark (아파치 스파크에서의 PARAFAC 분해 기반 텐서 재구성을 이용한 추천 시스템)

  • Im, Eo-Jin;Yong, Hwan-Seung
    • Journal of Korea Multimedia Society
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    • v.22 no.4
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    • pp.443-454
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    • 2019
  • In recent years, there has been active research on a recommender system that considers three or more inputs in addition to users and goods, making it a multi-dimensional array, also known as a tensor. The main issue with using tensor is that there are a lot of missing values, making it sparse. In order to solve this, the tensor can be shrunk using the tensor decomposition algorithm into a lower dimensional array called a factor matrix. Then, the tensor is reconstructed by calculating factor matrices to fill original empty cells with predicted values. This is called tensor reconstruction. In this paper, we propose a user-based Top-K recommender system by normalized PARAFAC tensor reconstruction. This method involves factorization of a tensor into factor matrices and reconstructs the tensor again. Before decomposition, the original tensor is normalized based on each dimension to reduce overfitting. Using the real world dataset, this paper shows the processing of a large amount of data and implements a recommender system based on Apache Spark. In addition, this study has confirmed that the recommender performance is improved through normalization of the tensor.

Acceleration Method for Integral Imaging Generation of Volume Data based on CUDA (CUDA를 기반한 볼륨데이터의 집적영상 생성을 위한 고속화 기법)

  • Park, Chan;Jeong, Ji-Seong;Park, Jae-Hyeung;Kwon, Ki-Chul;Kim, Nam;Yoo, Kwan-Hee
    • The Journal of the Korea Contents Association
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    • v.11 no.3
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    • pp.9-17
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    • 2011
  • Recently, with the advent of stereoscopic 3D TV, the activation of 3D stereoscopic content is expected. Research on 3D auto stereoscopic display has been carried out to relieve discomfort of 3D stereoscopic display. In this research, it is necessary to generate the elemental image from a lens array. As the number of lens in a lens array is increased, it takes a lot of time to generate the elemental image, and it will take more time for a large volume data. In order to improve the problem, in this paper, we propose a method to generate the elemental image by using OpenCL based on CUDA. We perform our proposed method on PC environment with one of Tesla C1060, Geforce 9800GT and Quadro FX 3800 graphics cards. Experimental results show that the proposed method can obtain almost 20 times better performance than recent research result[11].

Closed-form Localization of a coherently distributed single source with circular array (환형배열에서 닫힌 형식을 이용한 코히어런트 분산 단일음원의 위치 추정 기법)

  • Jung, Tae-Jin;Shin, Kee-Cheol;Park, Gyu-Tae;Cho, Sung-Il
    • The Journal of the Acoustical Society of Korea
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    • v.37 no.6
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    • pp.437-442
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    • 2018
  • In this paper, we propose a method for estimating the position of a source in a closed form when a single source has coherently distributed property against a circular array. When a sound source reaches a sensor through multipath environments, it is seen as a distributed source and can be represented by four variables: the nominal azimuth, nominal elevation, azimuth angular spread, elevation angular spread. Therefore, it requires a lot of computation by a search method such as DSPE (Distributed Source Parameter Estimator). In this paper, we propose a method of estimating the nominal azimuth and elevation angle in a closed form using correlation function and least squares method for fast position estimation. In particular, if the source is assumed as Gaussian distribution model, the standard deviation is also estimated in a closed form. In the simulation, the validity of the proposed method is confirmed by comparing with the DSPE.

The effect of coating wire on the performance of wire electrical discharge machining (코팅와이어가 와이어 방전가공 특성에 미치는 영향)

  • 임세환;김준현;김주현
    • Journal of the Korean Society for Precision Engineering
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    • v.21 no.2
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    • pp.177-185
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    • 2004
  • The machining performance of wire electrical discharge machining(WEDM), such as cutting speed, surface roughness and straightness depend on the electrode, and the machining parameters are diverse and affect each other. Therefore operator must have a lot of experiences of the parameter for the better machining performance in WEDM. An approach to minimize the time for determining of parameters setting is proposed. Based on the Taguchi method, the significant factors affecting the machining performance are determined. Types of electrodes are arranged at inner array in tables of orthogonal arrays so that we can estimate machining performances of each electrode. Coating wire shows better performances than brass wire in cutting speed but it produces poor surface roughness, and two wires shows similar performance in straightness

Demosaicking Method using High-order Interpolation with Parameters (매개변수를 갖는 고차원 보간법을 이용한 디모자이킹 기법)

  • Lee, Yeon-Kyung;Yoo, Hoon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.62 no.9
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    • pp.1276-1282
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    • 2013
  • This paper presents a demosaicking method based on high-order interpolation with parameters. Demosaicking is an essential process in capturing color images through a single sensor-array. Thus, a lot of methods including the Hamilton-Adams(HA) method has been studied in this literature. However, the image quality depends on various factors such as contrast and correlation in color space; existing algorithms depend on test images in use. Consequently, a new test image set was suggested to develop demosaicking algorithms properly. According to previous studies, the HA method shows high performances with the new test data set. In this paper, we improve the HA method using high-order interpolation with parameters. Also, we provide an analysis and formulations for the proposed method. To evaluate our method, we compare our method with the existing methods both objectively and subjectively. The experimental results indicate that the proposed method is superior to the existing methods.

Efficient Beam Steering Techniques in the Fixed Station (고정국에서의 효율적인 빔스티어링 기법)

  • Choi, Jun-sug;Hur, Chang-wu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.05a
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    • pp.826-828
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    • 2015
  • In this paper, Propose an efficient method that can operate at fixed stations Beam-Steering. Typical Beam-Forming techniques are performed using a delay time between the signal reaching each antenna array. The Beam-Forming method requires a lot of complexity and cost. This paper suggest a Beam-Steering method using a signal-to-noise ratio and a received signal strength. Analyzes the algorithm about proposed method.

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Taining Kit for Xilinx FPGA or ALTERA CPLD Digital Logic Design with Center Bridge Chipset Architecture (중앙 브릿지 칩셋을 갖춘 Xilinx FPGA, ALTERA CPLD 겸용 Digital Logic Design Training kit)

  • 전상현;정완영
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.907-910
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    • 2003
  • We have developed Logic Design Training Kit for studying, actual training, designing of FPGA(Xillinx) or CPLD(ALTERA CPLD), the Digital Logic Device. This training kit has 12 matrix keys, RS232 port for serial communication and uses LED array. six FND(Dynamic), LCD as display part. That is standard specification for digital logic training kit. Special point of this kit is that we make two logic device trainig kit. This two logic device kit have more smaller and simple architecture because only uses one chip. That chip already includes a lot of functions that need for training kit, such as : complex logic circuit needed the two kind of logic devices, 16 way of system clock deviding function, serial communication interrupt....etc. We called that one chip is Center Bridge Chipset ; Xillinx FPGA Spartan2. User can select between using one device of FPGA or CPLD, or uses both them. Because of, Center Bridge Chipset has profitable architecture. it can work as Logic Device's networking with Master-Slave connection When using both logic devices.

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Development of a Gear-shaped Manhole with Height Adjustment (기어형 높이 조절식 맨홀 개발)

  • Kim, Chang-Ho;Park, Joon-Hong;Choi, Jung-il
    • Journal of the Korean Society of Industry Convergence
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    • v.7 no.1
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    • pp.63-68
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    • 2004
  • There are a lot of manholes such as for water supply, sewage, telecommunication cable, traffic sign, electricity supply, and rainwater, etc. Conventional manholes installed on a road are impossible to adjust height, so that they should be entirely excavated to reinstall or repair. This entire excavation of a manhole causes too much time-consuming work, waste of resources, and obstruction of traffic. In this study, in order to solve the above mentioned problems, a cover, outer and inner parts of a manhole are integrated by gear-shaped parts located between outer and inner parts of a manhole. Mechanical design is performed to determine dimension of gear-shaped parts by Taguchi orthogonal array table. Cast molds for a gear-shaped manhole are also manufactured.

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