• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.259-261
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• 2015

In order to provide a safe and secure electronic navigational chart information services, AIS information, information on aids to navigation, maritime safety information, weather information, information on a variety of birds such as the data fused S-100 standards-based e-Navigation system should be established. S-101 ENC implement Rendering Engine analyzes the Drawing Instruction set generated by Portrayal Engine of the S-100 General Portrayal Model for is a job to be followed to establish the e-Navigation System to implement the S-101 ENC Should be. In this paper, we analyze the Drawing Instruction of the existing S-57 ENC and S-101 ENC is the basis for the implementation of the S-101 ENC.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.12
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• pp.2291-2299
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• 2008

Hall effect force sensors have been used to measure clamping force in conventional Electric Parking Brake(EPB) systems. Estimation of clamping force without the sensors has drawn attentions due to mounting space limitations and cost issues. Removing the sensor requires the estimation of the initial contact point where the clamping force is effectively applied to the brake pads. In this paper, we propose how to estimate the initial contact point finding the relation between the angular velocity of an actuator and the initial contact point. For force estimation a look-up table is used as a function of the displacement of parking cable from the initial contact point. The proposed method is validated by experiments. From the experimental results we observe that the proposed method satisfies the specifications. The designed method is also able to estimate clamping force although parking cables are loosened and brake pads are worn out. Applying the proposed method enables manufacturing of low cost EPB systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.2
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• pp.47-54
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• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.99-104
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• 2011

In this paper the approach of neural network was proposed which detects a variety of defects in the molded parts. In an attempt to improve the response of the system, It is designed to minimize the use of memory via LookUp table in software. The goal of these methods was to extract the features of samples in learning of neural networks, overcoming the algorithms of defects detection and classification. Through the learning of 500 sample patterns of molded parts, defects of 3% molded parts was detected and classified as the incorrect diameter parts. We expect that proposed approach is an effective alternative to save test time and cost for defect detection of a fine pattern within the molded parts.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.1
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• pp.18-27
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• 2002

This paper presents an implementation of digital high-performance speed sensorless control system of an induction motor drives with Direct Torque Control(DTC). The system consists of closed loop stator flux and torque observer, speed and torque estimators, two hysteresis controllers, an optimal switching look-up table, IGBT voltage source inverter, and TMS320C31 DSP controller board. The stator flux observer is based on the combined current and voltage model with stator flux feedback adaptive control for wide speed range. The speed estimator is using the model reference adaptive system(MRAS) with rotor flux linkages for speed turning signal estimation. In order to prove the suggested speed sensorless control algorithm, and to obtain a high-dynamic robust adaptive performance, we have some simulations and actual experiments at low(20rpm) and high(1000rpm) speed areas. The developed speed sensorless system are shown a good speed control response characteristic, and high performance features using 2.2[kW] general purposed induction motor.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.12
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• pp.691-700
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• 1999

This paper proposes a novel switching strategy of 1Mvar STATCON using cascade multilevel H-bridge inverter(HBI) for FACTS application. To control the reactive power instantaneously, the d-q dynamic system model is described and analyzed. A single pulse pattern based on the SHEM(Selective Harmonic Elimination Method) technique is determined from the look-up table to reduce the line current harmonics and a rotating fundamental frequency switching scheme is presented to adjust the DC voltage of each inverter capacitor at the same value. So the voltage unbalance problem between separately DC bus voltage is improved by using the proposed switching scheme. As a result, the presented inverter configuration not only reduces the system complexity by eliminating the isolation at the AC input side transformer but also improves the dynamic response to the step change of reactive power.

• International Journal of Automotive Technology
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• v.7 no.3
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• pp.369-375
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• 2006

This paper describes a simple proportional and integral control algorithm for a swirl motor controller and its application. The control algorithm may be complicated in order to have desired performance, such as low steady state errors, fast response time, and relatively low overshoot. At the same time, it should be compact so that it can be easily implemented on a low cost microcontroller, which has no floating-point calculation capability and low computing speed. These conflicting requirements are fulfilled by the proposed control algorithm which consists of a gain scheduling proportional controller and an anti-windup integral controller. The mechanical friction, which is caused by gears and a return spring, varies very nonlinearly according to the angular position of the system. This nonlinear static friction is overcome by the proportional controller, which has a two-dimensional look up gain table. It has error axis and angular position axis. The integral controller is designed not only to minimize the steady state error but also to avoid the windup effect, which may be caused by the saturation of a motor driver. The proposed control algorithm is verified by use of a commercial product to prove the feasibility of the algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.586-597
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• 2004

MAC (Medium Access Control) protocol is necessary for a OLT (Optical Line Termination) to allocate bandwidth to ONUs (Optical Network Units) dynamically in ATM PON (Passive Optical Network) operated in a kind of optical subscriber network having tree topology. The OLT collect information about ONUs and provide all permission with each ONU effectively by means of MAC protocol. Major functions of MAC protocol are composed of the algorism for distributing permission demanded by a ONU dynamically and allocation all permission used in APON properly. Sometimes MAC get to be a element of limiting the whole operation speed and occupy a most frequent operation part of the TC (Transmission Convergence) function module so it have to be designed to guarantee the best quality for each traffic. This paper introduce the way of implementation of a algorism which satisfy all of the upper renditions. This MAC algorism allocate bandwidth according to a number of working ONU and the information of the queue length dynamically and distribute permission for same interval to minimize delay variation of each ONU cell. MAC scheduler for the dynamic bandwidth allocation which is introduced in this paper has look-up table structure that makes programming possible. This structure is very suitable for implementation and operated in high speed because it require very simple and small chip size.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.6
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• pp.735-744
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• 2019

One of the key factors for recognition performance in the automatic target recognition for synthetic aperture radar imagery(SAR-ATR) system is reliability of the SAR target database. To achieve optimal performance, the database should be constructed using the images obtained under the same operating condition as the SAR sensor. However, it is impractical to have the extensive set of real-world SAR images, and thus those from the electro magnetic prediction tool with 3-D CAD models are suggested as an alternative where their reliability can be always questionable. In this paper, a method for similarity assessment between target SAR images is presented inspired by the fact that a target SAR image is mainly characterized by the features of scattering centers. The method is demonstrated using a variety of examples and quantitatively measures the similarity related to reliability. Its assessment performance is further compared with that of the existing metric, structural similarity(SSIM).

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.