• Journal of the Korean Institute of Gas
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• v.24 no.2
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• pp.15-21
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• 2020

Currently, in KS C IEC 60079-10-1, the leakage hole radius of secondary leakage is expressed as a recommendation. Underestimation of leak hole size can lead to underestimation of the calculated values for leak rates, and conservative calculations of leak hole sizes, which are considered for safety reasons, can be overestimated, resulting in an overestimated risk range. This too should be avoided. Therefore, a careful and balanced approach is necessary when estimating the size of leaking holes.Based on this logic, this study examines the stability by grasping the concentration inside the gas box when leaking dangerous substances as a result of experiments based on SEMI S6, an international safety standard applied in the semiconductor industry and The scope of explosion hazardous area was determined by applying the formula of KS C IEC 60079-10-1 according to SEMI F15 leak rate criteria and SEMI S6 leak rate criteria. Based on this, we will examine whether the exhaust performance needs to be improved as an alternative to FAB facilities that are difficult to apply to explosion hazards such as semiconductor industry.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1041-1043
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• 1993

Fuzzy logic based Control Theory has gained much interest in the industrial world, thanks to its ability to formalize and solve in a very natural way many problems that are very difficult to quantify at an analytical level. This paper shows a solution for treating membership function inside hardware circuits. The proposed hardware structure optimizes the memoried size by using particular form of the vectorial representation. The process of memorizing fuzzy sets, i.e. their membership function, has always been one of the more problematic issues for the hardware implementation, due to the quite large memory space that is needed. To simplify such an implementation, it is commonly [1,2,8,9,10,11] used to limit the membership functions either to those having triangular or trapezoidal shape, or pre-definite shape. These kinds of functions are able to cover a large spectrum of applications with a limited usage of memory, since they can be memorized by specifying very few parameters ( ight, base, critical points, etc.). This however results in a loss of computational power due to computation on the medium points. A solution to this problem is obtained by discretizing the universe of discourse U, i.e. by fixing a finite number of points and memorizing the value of the membership functions on such points [3,10,14,15]. Such a solution provides a satisfying computational speed, a very high precision of definitions and gives the users the opportunity to choose membership functions of any shape. However, a significant memory waste can as well be registered. It is indeed possible that for each of the given fuzzy sets many elements of the universe of discourse have a membership value equal to zero. It has also been noticed that almost in all cases common points among fuzzy sets, i.e. points with non null membership values are very few. More specifically, in many applications, for each element u of U, there exists at most three fuzzy sets for which the membership value is ot null [3,5,6,7,12,13]. Our proposal is based on such hypotheses. Moreover, we use a technique that even though it does not restrict the shapes of membership functions, it reduces strongly the computational time for the membership values and optimizes the function memorization. In figure 1 it is represented a term set whose characteristics are common for fuzzy controllers and to which we will refer in the following. The above term set has a universe of discourse with 128 elements (so to have a good resolution), 8 fuzzy sets that describe the term set, 32 levels of discretization for the membership values. Clearly, the number of bits necessary for the given specifications are 5 for 32 truth levels, 3 for 8 membership functions and 7 for 128 levels of resolution. The memory depth is given by the dimension of the universe of the discourse (128 in our case) and it will be represented by the memory rows. The length of a world of memory is defined by: Length = nem (dm(m)＋dm(fm) Where: fm is the maximum number of non null values in every element of the universe of the discourse, dm(m) is the dimension of the values of the membership function m, dm(fm) is the dimension of the word to represent the index of the highest membership function. In our case then Length=24. The memory dimension is therefore 128*24 bits. If we had chosen to memorize all values of the membership functions we would have needed to memorize on each memory row the membership value of each element. Fuzzy sets word dimension is 8*5 bits. Therefore, the dimension of the memory would have been 128*40 bits. Coherently with our hypothesis, in fig. 1 each element of universe of the discourse has a non null membership value on at most three fuzzy sets. Focusing on the elements 32,64,96 of the universe of discourse, they will be memorized as follows: The computation of the rule weights is done by comparing those bits that represent the index of the membership function, with the word of the program memor . The output bus of the Program Memory (μCOD), is given as input a comparator (Combinatory Net). If the index is equal to the bus value then one of the non null weight derives from the rule and it is produced as output, otherwise the output is zero (fig. 2). It is clear, that the memory dimension of the antecedent is in this way reduced since only non null values are memorized. Moreover, the time performance of the system is equivalent to the performance of a system using vectorial memorization of all weights. The dimensioning of the word is influenced by some parameters of the input variable. The most important parameter is the maximum number membership functions (nfm) having a non null value in each element of the universe of discourse. From our study in the field of fuzzy system, we see that typically nfm 3 and there are at most 16 membership function. At any rate, such a value can be increased up to the physical dimensional limit of the antecedent memory. A less important role n the optimization process of the word dimension is played by the number of membership functions defined for each linguistic term. The table below shows the request word dimension as a function of such parameters and compares our proposed method with the method of vectorial memorization[10]. Summing up, the characteristics of our method are: Users are not restricted to membership functions with specific shapes. The number of the fuzzy sets and the resolution of the vertical axis have a very small influence in increasing memory space. Weight computations are done by combinatorial network and therefore the time performance of the system is equivalent to the one of the vectorial method. The number of non null membership values on any element of the universe of discourse is limited. Such a constraint is usually non very restrictive since many controllers obtain a good precision with only three non null weights. The method here briefly described has been adopted by our group in the design of an optimized version of the coprocessor described in [10].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.

• Journal of Advanced Navigation Technology
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• v.19 no.5
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• pp.423-432
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• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.148-156
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• 2013

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through independently operating in each dedicated time periods. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple was 11 mV at 3.3V output voltage. Over/undershoot voltage was 10mV/19.6mV at 3.3V output voltage. The noise performance was simulated at 800mA and 100KHz load regulation. Core circuit can be implemented small size in $700{\mu}m{\times}800{\mu}m$ area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD $0.35{\mu}m$ technology.

• Korean Journal of Social Welfare
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• v.69 no.1
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• pp.125-145
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• 2017

The Purpose of this research is to draw implications of Multi-Functions of social welfare facilities on non-public social welfare delivery system especially in the rural area where there is not enough welfare infrastructure. The policy formation process of social welfare facilities was reviewed with 'Modified Policy Streams Framework" which combined Kingdon's Model with Mucciaroni's Model. Multi-Functions Policy of Social Welfare Facilities was led by the government with background of powerful President's initial stage of taking the power and finally legislated by amending Social Welfare Service Act in line with efficiency of non-public social welfare delivery system. However, the process did not represent the summation of needs originated from social work practice. The government just play the role of collecting some evidence underpinning the necessity of multi-functions of social welfare facilities and rearanging how to deploy the multi-functions policy. As the result the multi-functions policy is not activated and is not able to be the key criteria in expanding social welfare infrastructure. However, in spite of these limitation, the issue of multi-functions of social welfare facilities can cast the light on expanding infrastructure in the rural area where the gross size of area in larger in comparison to the district in the metropolitan city whereas residents are scattered because more number of social welfare facilities can not be the solution due to the limitation of finance and logic of efficiency.

• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of Korea Game Society
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• v.6 no.4
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• pp.47-53
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• 2006

In the game development differently with general software development, game planers, programers, and graphic designers, the specialists of the various fields, accomplished one team and they are advanced all to their goal. So it is very difficult for the development participants to communicate each other accurately and efficiently. For successful game development, all development participants should understand accurately the contents of the game design document. Specially the game mechanics as a major part of game design, requires the no-error contents, the no-error expression, and the no-error readings to all development participants because it contains almost game-play logic. It becomes more difficult for the development participants to understand accurately the game mechanics which becomes larger and complicated as the size of game development becomes larger. And configuration management of the game mechanics becomes more complicated and inefficient. In this paper, we propose a new representation method of game mechanics using UML notations for solving this problem. The proposed method satisfies the visual expression and the logical expression simultaneous for the requirements of the game mechanics because of UML notations. And the proposed method could be an efficient management of configuration because the management is based on the UML model management. The proposed representation of game mechanics of "Capture The Dude" game, shows good visual expression and good logical expression.

• Journal of the Korean Geotechnical Society
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• v.17 no.4
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• pp.289-299
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• 2001

본 연구는 균질 및 2개층 비균질지반에서 사질토지반 상에 놓인 정방형 기초의 극한지지력과 침하에 대하여 고찰하였다. 본 연구는 얕은기초의 거동에 대한 정방형 기초의 크기, 지반 상대밀도, 기초 폭에 대한 상부층의 두께 비(H/B), 상부층 아래 경계면의 경사($\theta$) 그리고 지반강성비의 영향을 규명하기 위하여 모형실험을 수행하였다. 동일 상대밀도에서 지지력 계수($N_{{\gamma}}$)는 일정하지 않으며 기초 폭에 직접적으로 관련되며 지지력계수는 기초 폭이 증가함에 따라 감소하였다. 기초크기의 영향과 구속압력의 영향을 고려하는 Ueno 방법에 의한 극한지지력의 예측값은 고전적인 지지력 산정식보다 더 잘 일치하며 그 값은 실험값의 65% 이상으로 나타났다. $\theta$=$0^{\circ}$인 2개층 지반의 결과에 근거하여, 극한지지력에 대한 하부층 지반의 영향을 무시할 수 있는 한계 상부층 두께는 기초 폭의 2배로 결정되었다. 그러나, 73%의 상부층 상대밀도인 경우는 침하비($\delta$B) 0.05 이하에서만 이 결과가 유효하였다. 경계면이 경사진 2개층 지반의 결과에 근거하여, 상부층의 상대밀도가 느슨할수록 그리고 상부층의 두께가 클수록 극한지지력에 대한 경계면 경사의 영향은 크지 않는 것으로 나타났다. 경계면의 경사가 증가함에 따른 극한침하량의 변화는 경계면이 수평인 경우($\theta$=$0^{\circ}$)를 기준으로 0.82~1.2(상부층 $D_{r}$=73%인 경우) 그리고 0.9~1.07(상부층 $D_{r}$=50%인 경우) 정도로 나타났다.Markup Language 문서로부터 무선 마크업 언어 문서로 자동 변환된 텍스트를 인코딩하는 경우와 같이 특정한 응용 분야에서는 일반 문자열에 대한 확장 인코딩 기법을 적용할 필요가 있을 수 있다.mical etch-stop method for the etching of Si in TMAH:IPA;pyrazine solutions provides a powerful and versatile alternative process for fabricating high-yield Si micro-membranes. the RSC circle, but also to the logistics system in the SLC circle. Thus, the RSLC model can maximize combat synergy effects by integrating the RSC and the SLC. With a similar logic, this paper develops "A Revised System of Systems with Logistics (RSSL)" which combines "A New system of Systems" and logistics. These tow models proposed here help explain several issues such as logistics environment in future warfare, MOE(Measure of Effectiveness( on logistics performance, and COA(Course of Actions) for decreasing mass and increasing velocity. In particular, velocity in logistics is emphasized.