• International Journal of Fuzzy Logic and Intelligent Systems
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• v.6 no.1
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• pp.10-14
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• 2006

Many clustering methods have been studied. For the most part of these methods may be needed to determine the number of clusters. But, there are few methods for determining the number of population clusters objectively. It is difficult to determine the cluster size. In general, the number of clusters is decided by subjectively prior knowledge. Because the results of clustering depend on the number of clusters, it must be determined seriously. In this paper, we propose an efficient method for determining the number of clusters using hybrid' self organizing map and new criterion for evaluating the clustering result. In the experiment, we verify our model to compare other clustering methods using the data sets from UCI machine learning repository.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.6 no.1
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• pp.47-51
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• 2006

Electrical resistance tomograpy (ERT) maps resistivity values of the soil subsurface and characterizes buried objects. The characterization includes location, size, and resistivity of buried objects. In this paper, truncated least squares (TLS) is presented for the solution of the ERT image reconstruction. Results of numerical experiments in ERT solved by the TLS approach is presented and compared to that obtained by the Gauss-Newton method.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.13 no.4
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• pp.324-335
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• 2013

This article presents the design, control, and implementation of a small quad-rotor system under the practical limitation of being cost effective for private use, such as in the cases of control education or hobbies involving radio-controlled systems. Several practical problems associated with implementing a small quad-rotor system had to be taken into account to satisfy this cost constraint. First, the size was reduced to attain better maneuverability. Second, the main control hardware was limited to an 8-bit processor such as an AVR to reduce cost. Third, the algorithms related to the control and sensing tasks were optimized to be within the computational capabilities of the available processor within one sampling time. A small quad-rotor system was ultimately implemented after satisfying all of the above practical limitations. Experimental studies were conducted to confirm the control performance and the operational abilities of the system.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.13 no.4
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• pp.254-268
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• 2013

For real-world clustering tasks, the input data is typically not easily separable due to the highly complex data structure or when clusters vary in size, density and shape. Kernel-based clustering has proven to be an effective approach to partition such data. In this paper, we provide an overview of several fuzzy kernel clustering algorithms. We focus on methods that optimize an fuzzy C-mean-type objective function. We highlight the advantages and disadvantages of each method. In addition to the completely unsupervised algorithms, we also provide an overview of some semi-supervised fuzzy kernel clustering algorithms. These algorithms use partial supervision information to guide the optimization process and avoid local minima. We also provide an overview of the different approaches that have been used to extend kernel clustering to handle very large data sets.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.163-172
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• 1995

In this paper, the bit-level 1-dimensionl systolic array for modular multiplication are designed. First of all, the parallel algorithms and data dependence graphs from Walter's Iwamura's methods based on Montgomery Algorithm for modular multiplication are derived and compared. Since Walter's method has the smaller computational index points in data dependence graph than Iwamura's, it is selected as the base algorithm. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays ale obtained and then are evaluated by various criteria. Modifying the array derived from 〔0,1〕 projection direction by adding a control logic and serializing the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for modular expandable and is good for fault tolerance due to unidirectional paths. And so, it is suitable for RSA Cryptosystem which deals with the large size and many consecutive message blocks.

• Journal of the Korea Society of Computer and Information
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• v.23 no.4
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• pp.1-8
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• 2018

In this paper, we propose an adaptive partition cache replacement policy and evaluate the performance of our scheme using various monitoring ratios to help lifetime extension of non-volatile main memory systems without performance degradation. The proposal combines conventional LRU (Least Recently Used) replacement policy and Early Eviction Zone (E2Z), which considers a dirty bit as well as LRU bits to select a candidate block. In particular, this paper shows the performance of non-volatile memory using various monitoring ratios and determines optimized monitoring ratio and partition size of E2Z for reducing the number of writebacks using cache hit counter logic and hit predictor. In the experiment evaluation, we showed that 1:128 combination provided the best results of writebacks and runtime, in terms of performance and complexity trade-off relation, and our proposal yielded up to 42% reduction of writebacks, compared with others.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.10
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• pp.19-26
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• 1992

Generally, When we calculate notch angle to eliminate some selected harmonics using PWM inverter, we put the previously analysed notch angle formed by look-up table into memory, or perform the program to claculate notch angle iteratively with Fourier series. But, these methods are very difficult to control the system in real-time. Now, in this paper, we propose a new method to calculate notch angle using Walsh series, design real-time logic circuits which can be applied in 3 phase circuits and make one chip to reduce complexity and size of circuits using VLSI design technique.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.9
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• pp.62-69
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• 1996

In this paper, the bit-level 1-dimensional systolic array for modular multiplication is designed. First of all, the parallel algorithm and data dependence graph from walter's method based on montgomery algorithm suitable for array design for modular multiplication is derived. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays are obtained and then are evaluated by various criteria. As it is modified the array which is derived form [0,1] projection direction by adding a control logic and it is serialized the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for expansile module and it is easy for fault tolerance due to unidirectional paths. It is suitable for RSA cryptosystem which deals iwth the large size and many consecutive message blocks.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.20-27
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• 1999

In many synthesis applications, the structure of the synthesized circuit is derived from its BDD functional representation. When synthesizing incompletely specified functions, it is useful to minimize the size of these BDDs using don't cares. In this paper, we present two BDD minimization heuristics that target these synthesis applications. Experimental results show that new techniques yield significantly smaller BDDs compared to existing techniques with manageable run-times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.118-129
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• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.