• Title/Summary/Keyword: Logic Tree

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Logic tree approach for probabilistic typhoon wind hazard assessment

  • Choun, Young-Sun;Kim, Min-Kyu
    • Nuclear Engineering and Technology
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    • v.51 no.2
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    • pp.607-617
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    • 2019
  • Global warming and climate change are increasing the intensity of typhoons and hurricanes and thus increasing the risk effects of typhoon and hurricane hazards on nuclear power plants (NPPs). To reflect these changes, a new NPP should be designed to endure design-basis hurricane wind speeds corresponding to an exceedance frequency of $10^{-7}/yr$. However, the short typhoon and hurricane observation records and uncertainties included in the inputs for an estimation cause significant uncertainty in the estimated wind speeds for return periods of longer than 100,000 years. A logic-tree framework is introduced to handle the epistemic uncertainty when estimating wind speeds. Three key parameters of a typhoon wind field model, i.e., the central pressure difference, pressure profile parameter, and radius to maximum wind, are used for constructing logic tree branches. The wind speeds of the simulated typhoons and the probable maximum wind speeds are estimated using Monte Carlo simulations, and wind hazard curves are derived as a function of the annual exceedance probability or return period. A logic tree decreases the epistemic uncertainty included in the wind intensity models and provides reasonably acceptable wind speeds.

A top-down iteration algorithm for Monte Carlo method for probability estimation of a fault tree with circular logic

  • Han, Sang Hoon
    • Nuclear Engineering and Technology
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    • v.50 no.6
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    • pp.854-859
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    • 2018
  • Calculating minimal cut sets is a typical quantification method used to evaluate the top event probability for a fault tree. If minimal cut sets cannot be calculated or if the accuracy of the quantification result is in doubt, the Monte Carlo method can provide an alternative for fault tree quantification. The Monte Carlo method for fault tree quantification tends to take a long time because it repeats the calculation for a large number of samples. Herein, proposal is made to improve the quantification algorithm of a fault tree with circular logic. We developed a top-down iteration algorithm that combines the characteristics of the top-down approach and the iteration approach, thereby reducing the computation time of the Monte Carlo method.

The Development of Logic of LTA(Logic Tree Analysis) for an Effective RCM Application of Rolling stock (철도차량의 효과적 RCM 적용을 위한 LTA로직 개발)

  • Song, Kee-Tae;Kim, Min-Ho;Baek, Young-Gu;Shin, Kun-Young;Lee, Key-Seo
    • Proceedings of the KSR Conference
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    • 2008.11b
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    • pp.1562-1569
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    • 2008
  • In this paper, the study on development of an applicable logic on the characteristics of Rolling stocks will be proposed. In general, this logic which means decision logic or LTA(Logic Tree Analysis) is used to analyze how the failure mode have an effects on the system. The effect would be categorized as safety, operational, economical, etc. To do this, based on the typical logics which have been applied to other industries, such as plants, aero, etc. This paper emphasizes two crucial parameters that is one cost the other customer service, that have an important role in railway system operation. In conclusion, as mentioned above as the logic for which could be effectively applied for the railway system(RST) would be developed.

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A Proof Method of Logic Programs in Parallel Environment (병렬화를 위한 논리 프로그램의 증명 방법)

  • 이원석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.3
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    • pp.425-438
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    • 1993
  • Due to the producer-consumer dependency of shared variables, the potential parallelism embeded in the logic programming language has not been fully examined. The method proposed in this paper eliminates the dependency of shared variables by introducing number-sequenced variables in expanding an AND-OR proof tree. Basically, the execution of a logic program can be divided into two phases : expanding an AND-OR tree and proving the tree by matching facts with leaf nodes. In the course of the first phase, a set of number-sequenced variables are produced by expanding an AND-OR tree in the breadth-first searching. Based on the information of number-sequence, each of them is verified in the second phase in order to prove the tree. Consequently, the proposed algorithm can explore more parallelism without the dependency of shared variables.

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A Modeling of Discrete Event System Using Temporal Logic Framework and Petri Net (시간논리 구조와 Petri Net의 합성방법을 사용한 이산사건 시스템의 모델링)

  • Kim, Jin-Kwon;Mo, Young-Seung;Ryu, Young-Guk;Hwang, Hyung-Soo
    • Proceedings of the KIEE Conference
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    • 1999.07b
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    • pp.838-840
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    • 1999
  • In this paper, modeling and analysis of discrete event systems by temporal logic frame works and petri net is considered. The reachability tree of the petri net can be used to solve the safeness, boundedness, conservation and coverability problems of discrete event systems. But the reachability tree of the petri net do not solve reachability and liveness problems in general. We proposed a method that synthesised the petri net and the temporal logic frameworks. This method slove some problems of petri net by logical representation of temporal logic frameworks.

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Method to Construct Feature Functions of C-CRF Using Regression Tree Analysis (회귀나무 분석을 이용한 C-CRF의 특징함수 구성 방법)

  • Ahn, Gil Seung;Hur, Sun
    • Journal of Korean Institute of Industrial Engineers
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    • v.41 no.4
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    • pp.338-343
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    • 2015
  • We suggest a method to configure feature functions of continuous conditional random field (C-CRF). Regression tree and similarity analysis are introduced to construct the first and second feature functions of C-CRF, respectively. Rules from the regression tree are transformed to logic functions. If a logic in the set of rules is true for a data then it returns the corresponding value of leaf node and zero, otherwise. We build an Euclidean similarity matrix to define neighborhood, which constitute the second feature function. Using two feature functions, we make a C-CRF model and an illustrate example is provided.

FMECA using Fault Tree Analysis (FTA) and Fuzzy Logic (결함수분석법과 퍼지논리를 이용한 FMECA 평가)

  • Kim, Dong-Jin;Shin, Jun-Seok;Kim, Hyung-Jun;Kim, Jin-O;Kim, Hyung-Chul
    • Proceedings of the KSR Conference
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    • 2007.11a
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    • pp.1529-1532
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    • 2007
  • Failure Mode, Effects, and Criticality Analysis (FMECA) is an extension of FMEA which includes a criticality analysis. The criticality analysis is used to chart the probability of failure modes against the severity of their consequences. The result highlights failure modes with relatively high probability and severity of consequences, allowing remedial effort to be directed where it will produce the greatest value. However, there are several limitations. Measuring severity of failure consequences is subjective and linguistic. Since The result of FMECA only gives qualitative and quantitative informations, it should be re-analysed to prioritize critical units. Fuzzy set theory has been introduced by Lotfi A. Zadeh (1965). It has extended the classical set theory dramatically. Based on fuzzy set theory, fuzzy logic has been developed employing human reasoning process. IF-THEN fuzzy rule based assessment approach can model the expert's decision logic appropriately. Fault tree analysis (FTA) is one of most common fault modeling techniques. It is widely used in many fields practically. In this paper, a simple fault tree analysis is proposed to measure the severity of components. Fuzzy rule based assessment method interprets linguistic variables for determination of critical unit priorities. An rail-way transforming system is analysed to describe the proposed method.

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Direct fault-tree modeling of human failure event dependency in probabilistic safety assessment

  • Ji Suk Kim;Sang Hoon Han;Man Cheol Kim
    • Nuclear Engineering and Technology
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    • v.55 no.1
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    • pp.119-130
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    • 2023
  • Among the various elements of probabilistic safety assessment (PSA), human failure events (HFEs) and their dependencies are major contributors to the quantification of risk of a nuclear power plant. Currently, the dependency among HFEs is reflected using a post-processing method in PSA, wherein several drawbacks, such as limited propagation of minimal cutsets through the fault tree and improper truncation of minimal cutsets exist. In this paper, we propose a method to model the HFE dependency directly in a fault tree using the if-then-else logic. The proposed method proved to be equivalent to the conventional post-processing method while addressing the drawbacks of the latter. We also developed a software tool to facilitate the implementation of the proposed method considering the need for modeling the dependency between multiple HFEs. We applied the proposed method to a specific case to demonstrate the drawbacks of the conventional post-processing method and the advantages of the proposed method. When applied appropriately under specific conditions, the direct fault-tree modeling of HFE dependency enhances the accuracy of the risk quantification and facilitates the analysis of minimal cutsets.

Resynthesis of Logic Gates on Mapped Circuit for Low Power (저전력 기술 매핑을 위한 논리 게이트 재합성)

  • 김현상;조준동
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.11
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    • pp.1-10
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    • 1998
  • The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.

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Black-Box Classifier Interpretation Using Decision Tree and Fuzzy Logic-Based Classifier Implementation

  • Lee, Hansoo;Kim, Sungshin
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.16 no.1
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    • pp.27-35
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    • 2016
  • Black-box classifiers, such as artificial neural network and support vector machine, are a popular classifier because of its remarkable performance. They are applied in various fields such as inductive inferences, classifications, or regressions. However, by its characteristics, they cannot provide appropriate explanations how the classification results are derived. Therefore, there are plenty of actively discussed researches about interpreting trained black-box classifiers. In this paper, we propose a method to make a fuzzy logic-based classifier using extracted rules from the artificial neural network and support vector machine in order to interpret internal structures. As an object of classification, an anomalous propagation echo is selected which occurs frequently in radar data and becomes the problem in a precipitation estimation process. After applying a clustering method, learning dataset is generated from clusters. Using the learning dataset, artificial neural network and support vector machine are implemented. After that, decision trees for each classifier are generated. And they are used to implement simplified fuzzy logic-based classifiers by rule extraction and input selection. Finally, we can verify and compare performances. With actual occurrence cased of the anomalous propagation echo, we can determine the inner structures of the black-box classifiers.