• Title/Summary/Keyword: Logic EEPROM

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Design of DC-DC converter for a logic process MTP memory IPs (로직 공정 기반의 MTP IP용 DC-DC 컨버터 설계)

  • Park, Heon;Lee, Seung-Hoon;Jin, Kyo-Hong;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.05a
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    • pp.832-836
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    • 2015
  • In this paper, a DC-DC converter is designed for logic process MTP (multi-time programmable) memory IPs using dual program voltage, which are used for analog trimming or storing chip IDs in sensor applications. The DC-DC converter supplies VPP (=5.25V), VNN (=-5.25V), and VNNL ($=2{\cdot}VNN/5$). It uses MOS capacitors and designed with only 3,3V devices. VPP and VNN are configured in two and five stages, respectively. And their pumping currents are $9.17{\mu}A$ and $9.7{\mu}A$, respectively.

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Embedded System for Automatic Condensation Control of the Car

  • Lee, Dmitriy;Bae, Yong-Wook;Lee, Neung-Ho;Seo, Hee-Don
    • Journal of Sensor Science and Technology
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    • v.21 no.1
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    • pp.21-27
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    • 2012
  • In this study, we designed an embedded system for automatic condensation control(ESCC) of the car. This system heats the car glasses as and when it is needed that makes driving safer and convenient. The system was built on an ATmega128L central processing unit(CPU), using high-performance electrically erasable programmable read-only memory(EEPROM) complex programmable logic device(CPLD) ATF1504AS, using which an ESCC algorithm has been proposed. The source code was written in C language. The algorithm of work was written using the dew-point table. This system not only clears the condensation on the glass but also averts condensation. The designed ESCC system begins working once the input information comes close to the dew-point table information. This device enables a wider field of view, thereby increasing safety.

Impact of LDD Structure on Single-Poly EEPROM Characteristics

  • Na, Kee-Yeol;Park, Mun-Woo;Kim, Kyung-Hoon;Kim, Nan-Soo;Kim, Yeong-Seuk
    • Journal of Electrical Engineering and information Science
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    • v.3 no.3
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    • pp.391-395
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    • 1998
  • The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8$\mu\textrm{m}$ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.

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