• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.185-186
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• 2015

This paper introduces general single PLL(Phase Locked Loop) algorithm and compares with proposed PLL method. The suggested PLL uses low pass filter to reduce high harmonics in real grid and uses feed forward method to compensate phase delay of the low pass filter.

• English & American cultural studies
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• v.14 no.1
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• pp.95-116
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• 2014

Paul Auster's The Locked Room, the third novel of The New York Trilogy, has been examined by many critics in terms of anti-detective fiction or postmodernism. However, this paper focuses upon how the author adopts and utilizes some key elements of the traditional detective novel and its literary tradition. Mystery storytelling is one of Auster's literary strategies and the theme of the double is another. For his novel Auster explores the theme of the double as in Poe's "William Wilson." In The Locked Room, the narrator "I" is described as a shadow of his childhood friend Fanshawe. After Fanshawe's disappearance "I" becomes a literary agent for his friend, and becomes a husband of his friend's wife and a father of his friend's child. Searching for information to write a biography of his friend, he realizes that his friend has always been living inside his skull condemned to a mystical solitude. When Fanshawe appears in the narrator's mind as an image of the door of a locked room, the locked room is also a metaphor for the closed consciousness of the narrator. In his strategy of mystery storytelling, Auster employs the quest of detective fiction as well as the irony of Oedipus the King, where the criminal pursued by the king turns out to be himself. The Locked Room starts with the mystery of Fanshawe's disappearance, and as the novel develops, the narrator pursues numerous clues about his biographical subject like a private eye. Ironically, however, he finds that the ghost of Fanshawe has always been with him and that this is inevitable. As the narrator resolves to quit his life as a double, he contrives to name a strange man Fanshawe as if he tries to turn his biographical subject into a fictional character in the same way Fanshawe has controlled the narrator like a character in Fanshawe's novel. Beaten by the fictional Fanshawe and recovering from a near-death experience, the narrator prepares for his final showdown with Fanshawe. The transcendence of his existence as a double is epitomized by his act to tear off the red notebook handed to him by Fanshawe, which confusingly delivers a message that a life is doomed to be a failure. The narrator's act to cut off Fanshawe's influence bespeaks his breaking out of his locked consciousness and a new start for his life with his own identity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.540-549
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• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Korean Journal of Optics and Photonics
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• v.26 no.6
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• pp.312-317
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• 2015

We investigate the effect of laser-resonator mode size on the output of a Yb:YAG laser that is mode-locked by a semiconductor saturable absorber mirror (SESAM). We demonstrate that the smaller the product of the mode sizes at a SESAM and at a Yb:YAG crystal, the more stable the mode-locked output is. Also, we found numerically that there is a resonator length at which the mode-locked output occurs, regardless of the thermal lens effect of a Yb:YAG.

• Journal of IKEEE
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• v.18 no.1
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• pp.19-24
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• 2014

We report stable, wideband, flat-topped, 10 GHz optical frequency comb generation from a semiconductor-based mode-locked ring laser with an intra-cavity high finesse Fabry-Perot etalon. We demonstrate a stable 10 GHz comb with greater than 200 lines within a spectral power variation below 1 dB, which is the largest value obtained from a similar mode-locked laser in our knowledge. Greater than 20 dB of the spectral peak to deep ratio at 0.02 nm resolution, ~92 femtosecond timing jitter over 1 kHz to 1 MHz range, and non-averaged time traces of pulses confirm very stable optical frequency comb lines.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.9
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• pp.461-466
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• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.309-312
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• 2008

We study signal characteristics of the injection-locked Fabry-Perot laser diodes(FP-LDs) for the development of a costeffective WDM-PON solution. The output power and system performance of WDM-PON using injection locked FP-LD are depend on optical characteristics of injection source. The effect of optical power and polarization state of the injection source experimentally investigated. We also measured BER characteristics of the directly modulated FPLD and its power penalty at the BER of $10^{-9}$.