• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.9
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• pp.1175-1182
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• 2013

The lock-in mode infrared thermography (IRT) technique has been developed to improve the detection capability of defects in materials with high thermal conductivity, and it has been shown to provide better detection capability than conventional active IRT. Therefore, to investigate the application of this technique to nuclear piping components, lock-in mode IRT tests were conducted on pipe specimens containing simulated wall-thinning defects. Phase images of the wall-thinning defects were obtained from the tests, and they were compared with thermal images obtained from conventional active IRT tests. It showed that the ability to size the detected wall-thinning defects in piping components was improved by using lock-in mode IRT. The improvement was especially apparent when detecting short and narrow defects and defects with slanted edges. However, the detection capability for shallow wall-thinning defects did not improve much when using lock-in mode IRT.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.8
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• pp.702-710
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• 2007

Direct numerical simulation (DNS) is performed to investigate suppressed wake transition and occurrence of lock-on in the wake of a circular cylinder disturbed by sinusoidal perturbation at the Reynolds number of 220 (A-mode instability regime). The sinusoidal perturbation, of which the frequency is near twice the natural shedding frequency, is superimposed on the free stream velocity. It is shown that the wake transition behind the circular cylinder can be suppressed due to the perturbation of the free stream velocity. This change causes a jump in the Strouhal number from the value corresponding to A-mode instability regime to the value corresponding to retarded wake transition regime (extrapolated from laminar shedding regime) in the Strouhal-Reynolds number relationship. As a result, vortex shedding frequency is locked on the perturbation frequency depending not on the natural shedding frequency but on the modified shedding frequency.

• Transactions of the Korean Society of Automotive Engineers
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• v.14 no.2
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• pp.9-15
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• 2006

Experiments are conducted to compare fuel economy of FTP-75 mode on two different lock-up conditions; (A) Lock-up on at engine speed of 1,200(rpm) and above for 3rd & 4th gear, (B) Lock-up on at engine speed of 1400rpm and above for 4th gear only. As a result, case A had better fuel economy about 2.75(%) than case B for FTP-75 mode. Simulation(CRUISE, AVL) study is also carried out in order to estimate the effect of Lock-up control strategy for vehicle fuel economy. The fuel economy simulation result agrees with the measured fuel economy within error of 2(%). The improved Lock-up control strategy is proposed by simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.46-52
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• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.186-187
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• 2006

The development of SFCL (Superconducting Fault Current Limiter) is getting more important as the power demand is increased rapidly. Up to now, several kinds of SFCL have been proposed and it is expected that they will be applied to appropriate position considering their own properties. Amongst those proposed SFCL, flux-lock type SFCL using the magnetic cancelation for current limiting has the advantages of overcoming the technical difficulties that other types of SFCLs have. In this paper, the integrated three-phase flux-lock type SFCL was fabricated and its operational modes were investigated through the short circuit tests. The operational mode were to divided into four mode according to the variation of the currents flowing into the secondary winding connected the superconducting elements and the speed of the quench generation. It was expected that the improvement of current limiting characteristics of the SFCL could be possible through control of the operational mode.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.523-530
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• 2005

This paper addresses sliding mode control (SMC) of the anti-lock braking system (ABS) with a compensator of model uncertainties such as vehicle parameter variation, unmodeled dynamics, and external disturbances. A sliding mode controller (SMC) is designed with a nominal vehicle model to achieve a desired wheel slip ratio. A disturbance observer (DOB) is introduced to compensate the model uncertainties and is designed with a transfer function of a hydraulic brake dynamics. Through simulations on the model uncertainties, it is verified that the sliding mode control with the DOB can give the simulation results better than the sliding mode control without the DOB.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.4 s.181
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• pp.44-51
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• 2006

This paper addresses sliding mode control of the anti-lock braking system (ABS) with a disturbance observer for model uncertainties such as vehicle parameter variation, un-modeled dynamics, and external disturbances. By using a nominal vehicle model, a sliding mode controller is designed to achieve a desired wheel slip ratio for ABS control. To compensate the model uncertainties, a disturbance observer is introduced with the help of a transfer function of a hydraulic brake dynamics. A proposed sliding mode controller with a disturbance observer is evaluated through simulations for model uncertainties. The simulation results show that the disturbance observer can enhance performances of sliding mode control for ABS.

• Transactions of the Korean Society of Automotive Engineers
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• v.21 no.1
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• pp.78-85
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• 2013

This paper presents the sliding mode control methods for anti-lock brake system (ABS) with the friction force observer. Using a simplified quarter car model, the sliding mode controller for ABS is designed to track the desired wheel slip ratio. Here, new method to find the desired wheel slip ratio which produces the maximum friction force between road and tire is suggested. The desired wheel slip ratio is varying according road and tire conditions to produce maximum friction force. In order to find optimum desired wheel slip ratio, the sliding mode observer for friction force is used. The proposed sliding mode controller with observer is evaluated in simulation, and the control design is shown to have high performance on roads with constant and varying adhesion coefficients.