• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.11-17
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• 2009

The drop impact reliability comes to be important for evaluation of the life time of mobile electronic products such as cellular phone. The drop impact reliability of solder joint is generally affected by the kinds of pad and reflow number, therefore, the reliability evaluation is needed. Drop impact test proposed by JEDEC has been used as a standard method, however, which requires high cost and long time. The drop impact reliability can be indirectly evaluated by using high speed shear test of solder joints. Solder joints formed on 3 kinds of surface finishes OSP (Organic Solderability Preservation), ENIG (Electroless Nickel Immersion Gold) and ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) was investigated. The shear strength was analysed with the morphology change of intermetallic compound (IMC) layer according to reflow number. The layer thickness of IMC was increased with the increase of reflow number, which resulted in the decrease of the high speed shear strength and impact energy. The order of the high speed shear strength and impact energy was ENEPIG > ENIG > OSP after the 1st reflow, and ENEPIG > OSP > ENIG after 8th reflow.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Proceedings of the KWS Conference
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• 2005.06a
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• pp.54-56
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• 2005

Ultrasonic soldering using of Si-wafer to FR-4 PCB atroom temperature was investigated. Sn3.5Ag foil rolled $100{\mu}m$ was used for solder. The UBM of Si-die was Cu/ Ni/ Al from top to bottom and its thickness was $0.4{\mu}m$, $0.4{\mu}m$, $0.3{\mu}m$ respectively. Pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom and its thickness was $0.05{\mu}m$, $5{\mu}m$, $18{\mu}m$ respectively. The ultrasonic soldering time was changed from 0.5sec to 3.0sec and its power 1400W. As experimental result, reliable bond joint by ultrasonic at room temperature was obtained. The shear strength increased with soldering time up to 2.5 sec. That means at 2.5sec, the shear strength showed maximum rate of 65.23N. The strength decreased to 33.90N at 3.0 sec because the cracks generated along the intermetallic compound between Si-wafer and Sn-3.5mass%Ag solder. intermetallic compound produced by ultrasonic between the solder and the Si-die was $(Cu, Ni)_{6}Sn_{5}$ and the intermetallic compound between solder and pad on FR-4 was $(Ni, Cu)_{3}Sn_{4}$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.195-201
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• 2000

Current Status: Good Electrical performance for high speed device, Solder joint reliability-Passed 1600 cycles for 4M SRAM(3.27mm DNP),-Passed 400 cycles for large die(5.71 mm DNP), Future Plan: Improving Board Level Reliability for large die size, Lead free solder evaluation.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.6-11
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• 2010

This research is the result for studding about the IR Rework station which is using a multi-wave IR-heater for soldering and de-soldering on the substrate such as PCB. This IR repair and reflow system is increasing the temperature on the target area under stable temperature control following setting point melting point of solder and lead free solder using IR-heater. So this system is not giving any therrna1 damage on the target PCB and components even closed components. The soldering and de-soldering quality is evaluated through the actual test.

• Vacuum Magazine
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• v.1 no.1
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• pp.17-20
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• 2014

This article introduces the basic concepts of various soft X-ray spectroscopies in the study of surface and interface electronic structures. Especially, recent results of X-ray photoelectron spectroscopy experiments on organic/inorganic thin films and a lead-free solder alloys will be discussed. Soft X-ray spectroscopies to understand the chemical and electrical properties would be of broad interest in the vacuum science communities.

• Proceedings of the KWS Conference
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• 2004.05a
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• pp.73-74
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• 2004

Sn-Pb계 유연 솔더는 오랜 기간동안 전자기기의 가장 유효한 접합재료로 사용되어 왔다 그러나, 근년. 솔더를 사용한 전자기기의 폐기 시에 산성비에 의해 솔더중에 함유된 납(Pb) 성분이 용출되어 지하수를 오염시키고 이것이 인체에 흡수되면 지능저하, 생식기능저하 등 인체에 해를 미치는 환경오염 물질로 지적되고 있다. (중략)

• Proceedings of the KWS Conference
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• 2005.06a
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• pp.28-30
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• 2005

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.05a
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• pp.136-136
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• 2012

최근 전자제품의 크기가 소형화, 고성능화 되어감에 따라 전자제품을 구성하는 부품 크기도 작아지고, 배선의 피치 또한 미세화 되고 있다. 따라서 패키징 과정도 미세하고 정확한 제어를 필요로 하게 되었으며, 전해도금을 통한 정밀 패키징 공정이 도입되고 있다. 그러나 기존에는 패키징용 메인기판과 부품을 연결하는 솔더는 기존의 Sn-Pb 조성의 납을 포함하는 소재가 사용되었다. 하지만 납의 환경적 문제에 의해 사용을 금지하게 된 상태로 이를 대체하기 위한 무연 조성의 솔더가 연구되고 있다.

• Journal of the Korean institute of surface engineering
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• v.36 no.5
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• pp.386-392
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• 2003

The electroplating process for a solder bump which can be applied for a flip chip was studied. Si-wafer was used for an experimental substrate, and the substrate were coated with UBM (Under Bump Metallization) of Al(400 nm)/Cu(300 nm)Ni(400 nm)/Au(20 nm) subsequently. The compositions of the bump were Sn-Cu and eutectic Sn-Pb, and characteristics of two bumps were compared. Experimental results showed that the electroplated thickness of the solders were increased with time, and the increasing rates were TEX>$0.45 <\mu\textrm{m}$/min for the Sn-Cu and $ 0.35\mu\textrm{m}$/min for the Sn-Pb. In the case of Sn-Cu, electroplating rate increased from 0.25 to $2.7\mu\textrm{m}$/min with increasing current density from 1 to 8.5 $A/dm^2$. In the case of Sn-Pb the rate increased until the current density became $4 A/dm^2$, and after that current density the rate maintains constant value of $0.62\mu\textrm{m}$/min. The electro plated bumps were air reflowed to form spherical bumps, and their bonded shear strengths were evaluated. The shear strength reached at the reflow time of 10 sec, and the strength was of 113 gf for Sn-Cu and 120 gf for Sn-Pb.