• 한국전기전자재료학회논문지
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• 제22권2호
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1103-1107
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• 2007

Highly efficient organic electroluminescent devices (OLEDs) based on 4,7- diphenyl-1, 10- phenanthroline (BPhen) as the electron transport layer (ETL), tris (8-hydroxyquinoline) aluminum ($Alq_3$) as the emission layer (EML) and N,$\acute{N}$-bis-[1-naphthy(-N,$\acute{N}$diphenyl-1,1´-biphenyl-4,4´-diamine)] (NPB) as the hole transport layer (HTL) were developed. The typical device structure was glass substrate/ ITO/ NPB/$Alq_3$/ BPhen/ LiF/ Al. Since BPhen possesses a considerable high electron mobility of $5\;{\times}\;10^{-4}\;cm^2\;V^{-1}\;s^{-1}$, devices with BPhen as ETL can realize an extremely high luminous efficiency. By optimizing the thickness of both HTL and ETL, we obtained a highly efficient OLED with a current efficiency of 6.80 cd/A and luminance of $1361\;cd/m^2$ at a current density of $20\;mA/cm^2$. This dramatic improvement in the current efficiency has been explained on the principle of charge balance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.339-339
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• 2012

현재 MOS 소자에 사용되고 있는 $SiO_2$ 산화막은 그 두께가 얇아짐에 따라 Gate Leakage current와 여러 가지 신뢰성 문제가 대두되고 있고, 이를 극복하고자 High-k물질을 사용하여 기존에 발생했던 Gate Leakage current와 신뢰성 문제를 해결하고자 하고 있다. 본 실험에서는 High-k(hafnium) Gate Material에 온도 변화를 주었을 때 여러 가지 전기적인 특성 변화를 보는 방향으로 연구를 진행하였다. 기본적인 P-Type Si기판을 가지고, 그 위에 있는 자연적으로 형성된 산화막을 제거한 후 Hafnium Gate Oxide를 Atomic Layer Deposition (ALD)를 이용하여 증착하고, Aluminium을 전극으로 하는 MOS-Cap 구조를 제작한 후 FGA 공정을 진행하였다. 마지막으로 $300^{\circ}C$, $450^{\circ}C$로 30분정도씩 Annealing을 하여, 온도 조건이 다른 3가지 종류의 샘플을 준비하였다. 3가지 샘플에 대해서 각각 I-V (Gate Leakage Current), C-V (Mobile Charge), Interface State Density를 분석하였다. 그 결과 Annealing 온도가 올라가면 Leakage Current와 Dit(Interface State Density)는 감소하고, Mobile Charge가 증가하는 것을 확인할 수가 있었다. 본 연구는 향후 High-k 물질에 대한 공정 과정에서의 다양한 열처리에 따른 전기적 특성의 변화 대한 정보를 제시하여, 향후 공정 과정의 열처리에 대한 방향을 잡는데 도움이 될 것이라 판단된다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.72-72
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• 2010

Recent development of organic solar cell approaches the level of 8% power conversion efficiency by the introduction of new materials, improved material engineering, and more sophisticated device structures. As for interface engineering, various interlayer materials such as LiF, CaO, NaF, and KF have been utilized between Al electrode and active layer. Those materials lower the work function of cathode and interface barrier, protect the active layer, enhance charge collection efficiency, and induce active layer doping. However, the addition of another step of thin layer deposition could be a little complicated. Thus, on a typical solar cell structure of Al/P3HT:PCBM/PEDOT:PSS/ITO glass, we used Li:Al alloy electrode instead of Al to render a simple process. J-V measurement under dark and light illumination on the polymer solar cell using Li:Al cathode shows the improvement in electric properties such as decrease in leakage current and series resistance, and increase in circuit current density. This effective charge collection and electron transport correspond to lowered energy barrier for electron transport at the interface, which is measured by ultraviolet photoelectron spectroscopy. Indeed, through the measurement of secondary ion mass spectroscopy, the Li atoms turn out to be located mainly at the interface between polymer and Al metal. In addition, the chemical reaction between polymer and metal electrodes are measured by X-ray photoelectron spectroscopy.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.211.1-211.1
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• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.

• 대한화학회지
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• 제36권4호
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• pp.477-484
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• 1992

Y123 초전도체 및 Y124 초전도체 결정 구조에서 사슬과 층에 존재하는 구리의 화학결합 및 전자 성질을 반경험적 분자 궤도론인 ASED-MO로 계산하여 VEP(valence electron population), DOS(density of state) 및 COOP(crystal orbital overlap population)로써 고찰하였다. 또한 구리 원자의 환경 효과를 알아보기 위하여 하전 덩어리 모델에 수소의 점전하가 있는 경우와 점전하가 없는 경우를 도입하였다. ASED-MO 계산 결과로 부터, Y123 초전도체 및 Y124 초전도체의 사슬에 존재하는 구리 원자는 전자 받게 역할을 하며, 층에 존재하는 구리 원자는 전자 주게 역할을 한다는 것을 알 수 있었다. 점전하가 없는 Y123 초전도체 및 Y124 초전도체의 사슬에 존재하는 구리의 산화 상태는 층에 존재하는 구리의 산화 상태보다도 더 크다. Y123 초전도체의 층에 존재하는 구리 원자의 산화 상태는 Y124 초전도체의 층에 존재하는 구리 원자의 산화 상태보다도 더 크다. 그리고 Y123 초전도체의 사슬과 층에 존재하는 구리 원자는 주위 환경에 크게 영향을 받지 않으며, Y124 초전도체의 사슬과 층에 존재하는 구리 원자의 경우 Y123 초전도체와 다르게 주위 환경에 크게 영향을 받는다는 것을 알 수 있었다. 또한 Cu1-O4, Cu2-O4의 전자분포와 결합성은 Y123 초전도체와 Y124 초전도체가 다르게 나타났다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.458-458
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• 2011

Graphene, a single atomic layer of sp2-bonded carbon, shows substantial potential for various applications. Chemical manipulation of its electronic properties will be of great importance. In this study, we have investigated interaction between graphene and organic molecular layer of tetrafluorotetracyanoquinodimethane (F4-TCNQ), a strong electron acceptor. F4-TCNQ films of varying thickness were evaporated onto graphene mechanically exfoliated on SiO2/Si substrates. F4-TCNQ molecules increase the frequencies of Raman G and 2D bands of graphene while decreasing the linewidth of G band and 2D/G intensity ratio, which is consistent with increase of hole density in graphene. These results exemplify the possibility of chemical tuning of electronic properties of graphene.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.335-338
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• 2000

Carbon is an attractive candidate for use in eletrochemical supercapacitors that depend on charge storage in the electrode/electrolyte international double layer. Property of an electrical double layer capacitor depend both on the technique used to prepare the electrode and on the current collector structure. The study is to research that V$_2$O$_{5}$-flyash-AC composite electrode for supercapacitor. The discharge capacitance of V$_2$O$_{5}$-flyash-AC(70wt%) in 1st and 50th cycle was 18.6F/g and 15.13F/g at current density of 0.5mA/cm$^2$. The discharge process of V$_2$O$_{5}$-flyash (3 : 97)-AC composite electrode is larger than that others.thers.