• Journal of KIISE:Software and Applications
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• v.29 no.12
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• pp.957-965
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• 2002

Garbage collection in the CLDC typically employs a stop-the-world GC algorithm which is performing a complete garbage collection when needed. This technique is unsuitable for the interactive Java embedded system because this can lead to long and unpredictable delays. In this paper, We present a garbage collection algorithm which reduces the average delay time and supports the interactive environment. Our garbage collector is composed of the allocator and the collector. The allocator determines the allocation position of free-list according to object size, and the collector uses an incremental mark-sweep algorithm. The garbage collector is called periodically by the thread scheduling policy and the allocator allocates the objects of marked state during collection cycle. Also, we introduce a color toggle mechanism that changes the meaning of the bit patterns at the end of the collection cycle. We compared the performance of our implementation with stop-the-world mark-sweep GC. The experimental results show that our algorithm reduces the average delay time and that it provides uniformly low response times.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.108-116
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• 1989

The simulator described here-LOSIM(LOgic SIMulator)-was developed to verify the logic design for VLSI(Very Large Scale Integrated) circuits at mixed level. In this paper, we present a modeling approach to obtain more accurate results than conventional logic simulators [5-6,9] for general elements, functional elements, transmission gates and tri-state gates using eight signal values and two gignal strengths. LOSIM has the capability which can perform timing and hazard analysis by using assignable rise and fall delays. We also prosent an efficient algorithm to accurately detectdynamic and static hazards which may be caused by the circuit delays. Our approach is based on five logic values and the scheduled time. LOSIM has been implemented on a UN-3/160 workstation running Berkeley 4.2 UNIX, and the program is written in C language. Static RAM cell and asynchronous circuit are illustrated as an example.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.30-36
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• 2010

Due to the scaling of process parameters, the density on chips has been increasing. This trend increases not only the temperature on chips but also the gradient of the temperature depending on distances. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees that are generated through the DME(Deferred Merge Embedding) algorithm. We have implemented the proposed technique using C language for the performance evaluation. The experimental results show that the clock insertion point generated by the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

• THE INTERNATIONAL COMMERCE & LAW REVIEW
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• v.12
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• pp.253-276
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• 1999

CISG articles 34 and 37 clearly allow the seller to cure any nonconformity in documents of sale or performance prior to the date for delivery if it does not cause the buyer unreasonable inconvenience or unreasonable expense. CISG article 48 allows a seller to cure the performance even after the date for delivery if it does not cause the buyer unreasonable delay, unreasonable inconvenience or unreasonable uncertainty of reimbursement by the seller of expenses advanced by the buyer. The wording any failure to perform is broad enough to include a delay. The seller's right to cure relates to all his obligations. The seller may remedy 'any failure to perform his obligations'. This language is broad enough to include a defect in documents. In some cases the fact that the seller is able and willing to remedy the non-conformity of the goods without inconvenience to the buyer, may mean that there would be no fundamental breach unless the seller failed to remedy the non-conformity within an appropriate time. It cannot generally be said what unreasonable inconvenience means. This can only be decided on a case-by-case basis. The seller must bear the costs involved in remedying a failure to perform. The curing of a failure to perform may have influence on the amount of the damage claimed. Insofar as the seller has the right to cure, the buyer is in that case obliged to accept the cure. If he refuses to do so, he can neither avoid the contract nor declare a reduction in price. This rule clearly shows the underlying concept of the CISG, to keep to the contract, if possible. Should the buyer requires delivery of substitute goods and the seller offers repair, it depends on the expense each case. The buyer must receive the request or notice by the seller. The relationship between the seller's right to cure and the buyer's right to avoid the contract is unclear. The buyer's right to avoid the contract should not nullify the seller's right to cure if the offer is reasonable. In addition, whether a breach is fundamental should be decided in the right of the seller's offer to cure.

• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.5 no.1
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• pp.102-107
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• 1994

Recently several studies showed a strong and specific association of Attention-Deficit Hyperactivity Disorder(ADHD) and generalized resistance to thyroid hormone(GRTH). The recommandation that all children with ADHD be screened for GRTH is an newer controversial issue in child psychiatric field. Author examined thyroid indices(T3, T4, TSH) and clinical characteristics in the 51 clinical populations with ADHD, developmental delay, and language disorders. The results are that 11 cases were out of the normal range of both T2 and T4 inspite of normal TSH. This finding is suggestive of the finding of GRTH cases. Therefore I suggest that child psychiatrist should pay attention to ADHD symptoms secondary to GRTH and that all children with familial ADHD and developmental delay(including launguage disorder) be screened for thyroid abnormalities.

• Journal of The Korean Society of Inherited Metabolic disease
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• v.13 no.2
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• pp.104-110
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• 2013

Purpose: Phenylketonuria (PKU) is the first inherited metabolic disease of which treatment is known. We performed this study to find out clinical symptoms and prognosis of tetrahydrobiopterin (BH4) responsive PKU patients and genetic relation. Methods: Clinical, biochemical, genetic analysis were done retrospectively in 23 patients diagnosed BH4 responsive PKU in Soonchunhyang University Hospital from March 2000 to September 2012. Results: Patients were classified to mild hyperphenylalaninemia and mild phenylketonuria with initial plasma phenylalanine level below 20 mg/dL. After BH4 loading, blood phenylalanine decrease level ranged between 37% and 99%. Initial treatment with low phenylalanine formula or BH4 was started before 2 month after birth except 2 patients. And one of them resulted in developmental delay in language and social activity. The others showed satisfactory progress without developmental delay. In genetic analysis, of 46 allele, R241C allele mutation was identified most commonly (41%). R241C/A259T, R241C/R243Q, R241C/V388M, R241C/T278I was detected in 5 (21.7%), 3 (13%), 2 (8%), 2 (8%) patients, respectively. Conclusion: R241C mutation was detected most frequently in this study group and R243Q mutation which is known to be prevalent in Korean PKU patients was found in 4 patients (8.6%). Early diagnosis and treatment is important in PKU patients.

• Journal of Digital Convergence
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• v.16 no.12
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• pp.309-315
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• 2018

In this paper, propose an efficient arc detection and control method to achieve fast machining speed, improved precision and surface roughness in discharge machining, especially for carbide and hard material processing and metal processing using discharge phenomenon as energy. A single discharge waveform is divided into three sections of Td (Time-Delay), Ton (Time-on) and Toff (Time-off) and the gate control timing is simulated using the HDL language. In this paper, we analyze the effect of the gap between the electrode and the workpiece on the machining results by determining the operation of the servo mechanism by sampling the Td section through the comparator circuit. As a result of the analysis, the Td section of the formed waveform was more precisely sampled at a high speed and the results were improved when applied to the gap control between the electrode and the workpiece.

• Journal of the Korea Convergence Society
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• v.13 no.3
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• pp.43-54
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• 2022

Simultaneous translation is online decoding to translates with only subsentence. The goal of simultaneous translation research is to improve translation performance against delay. For this reason, most studies find trade-off performance between delays. We studied the experiments of the fixed policy-based simultaneous translation in Korean. Our experiments suggest that Korean tokenization causes many fragments, resulting in delay compared to other languages. We suggest follow-up studies such as n-gram tokenization to solve the problems.