• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.168-175
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• 2013

Color consistency in stereoscopic contents is important for 3D display systems. Even with a stereo camera of the same model and with the same hardware settings, complex color discrepancies occur when acquiring high quality stereo images. In this paper, we propose an integrated color matching method that use cumulative histogram in global matching and estimated 3D-distance for the stage of local matching. The distance between the current pixel and the target local region is computed using depth information and the spatial distance in the 2D image plane. The 3D-distance is then used to determine the similarity between the current pixel and the target local region. The overall algorithm is described as follow; First, the cumulative histogram matching is introduced for reducing global color discrepancies. Then, the proposed local color matching is established for reducing local discrepancies. Finally, a weight-based combination of global and local matching is computed. Experimental results show the proposed algorithm has improved global and local error correction performance for stereoscopic contents with respect to other approaches.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.1 s.307
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• pp.45-52
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• 2006

In this paper, a real-time stereoscopic image conversion method using a single frame from a 2-D image is proposed. The Stereoscopic image is generated by creating depth map using vortical position information and parallax processing. For a real-time processing of stereoscopic conversion and reduction of hardware complexity, it uses image sampling, object segmentation by standardizing luminance and depth map generation by boundary scan. The proposed method offers realistic 3-D effect regardless of the direction, velocity and scene conversion of the 2-D image. It offers effective stereoscopic conversion using images suitable conditions assumed in this paper such as recorded image at long distance, landscape and panorama photo because it creates different depth sense using vertical position information from a single frame. The proposed method can be applied to still image because it uses a single frame from a 2-D image. The proposed method has been evaluated using visual test and APD for comparing the stereoscopic image of the proposed method with that of MTD. It is confirmed that stereoscopic images conversed by the proposed method offers 3-D effect regardless of the direction and velocity of the 2-D image.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.78-86
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• 1999

In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.28-34
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• 2012

Various feature extraction algorithms are widely applied to real-time image processing applications for extracting significant features from images. Feature extraction algorithms are mostly combined with image processing algorithms mostly for image tracking and recognition. Feature extraction function is used to supply feature information to the other image processing algorithms and it is mainly implemented in a preprocessing stage. Nowadays, image processing applications are faced with embedded system implementation for a real-time processing. In order to satisfy this requirement, it is necessary to reduce execution time so as to improve the performance. Reducing the time for executing a feature extraction function dose not only extend the execution time for the other image processing algorithms, but it also helps satisfy a real-time requirement. This paper explains FAST (Feature from Accelerated Segment Test algorithm) of E. Rosten and presents FPGA-based embedded hardware accelerator architecture. The proposed acceleration scheme can be implemented by using approximately 2,217 Flip Flops, 5,034 LUTs, 2,833 Slices, and 18 Block RAMs in the Xilinx Vertex IV FPGA. In the Modelsim - based simulation result, the proposed hardware accelerator takes 3.06 ms to extract 954 features from a image with $640{\times}480$ pixels and this result shows the cost effectiveness of the propose scheme.

• Journal of Ginseng Research
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• v.46 no.3
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• pp.418-425
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• 2022

Background: Sorafenib is effective in treating hepatoma, but most patients develop resistance to it. STAT3 signaling has been implicated in sorafenib resistance. Artesunate (ART) and 20(R)-ginsenoside Rg3 (Rg3) have anti-hepatoma effects and can inhibit STAT3 signaling in cancer cells. This study aimed to evaluate the effects of Rg3 in combination with ART (Rg3-plus-ART) in overcoming sorafenib resistance, and to examine the involvement of STAT3 signaling in these effects. Methods: Sorafenib-resistant HepG2 cells (HepG2-SR) were used to evaluate the in vitro anti-hepatoma effects of Rg3-plus-ART. A HepG2-SR hepatoma-bearing BALB/c-nu/nu mouse model was used to assess the in vivo anti-hepatoma effects of Rg3-plus-ART. CCK-8 assays and Annexin V-FITC/PI double staining were used to examine cell proliferation and apoptosis, respectively. Immunoblotting was employed to examine protein levels. ROS generation was examined by measuring DCF-DA fluorescence. Results: Rg3-plus-ART synergistically reduced viability of, and evoked apoptosis in HepG2-SR cells, and suppressed HepG2-SR tumor growth in mice. Mechanistic studies revealed that Rg3-plus-ART inhibited activation/phosphorylation of Src and STAT3 in HepG2-SR cultures and tumors. The combination also decreased the STAT3 nuclear level and induced ROS production in HepG2-SR cultures. Furthermore, overactivation of STAT3 or removal of ROS diminished the anti-proliferative effects of Rg3-plus-ART, and removal of ROS diminished Rg3-plus-ART's inhibitory effects on STAT3 activation in HepG2-SR cells. Conclusions: Rg3-plus-ART overcomes sorafenib resistance in experimental models, and inhibition of Src/STAT3 signaling and modulation of ROS/STAT3 signaling contribute to the underlying mechanisms. This study provides a pharmacological basis for developing Rg3-plus-ART into a novel modality for treating sorafenib-resistant hepatoma.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1172-1179
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• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.

• KIPS Transactions on Software and Data Engineering
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• v.11 no.1
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• pp.51-58
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• 2022

Drivable area detection, one of the main functions of advanced driver assistance systems, means detecting an area where a vehicle can safely drive. The drivable area detection is closely related to the safety of the driver and it requires high accuracy with real-time operation. To satisfy these conditions, V-disparity-based method is widely used to detect a drivable area by calculating the road disparity value in each row of an image. However, the V-disparity-based method can falsely detect a non-road area as a road when the disparity value is not accurate or the disparity value of the object is equal to the disparity value of the road. In a road environment including vegetation, such as a highway and a country road, the vegetation area may be falsely detected as the drivable area because the disparity characteristics of the vegetation are similar to those of the road. Therefore, this paper proposes a drivable area detection method and hardware architecture with a high accuracy in road environments including vegetation areas by reducing the number of false detections caused by V-disparity characteristic. When 289 images provided by KITTI road dataset are used to evaluate the road detection performance of the proposed method, it shows an accuracy of 90.12% and a recall of 97.96%. In addition, when the proposed hardware architecture is implemented on the FPGA platform, it uses 8925 slice registers and 7066 slice LUTs.