• Journal of Information Processing Systems
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• v.15 no.3
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• pp.570-592
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• 2019

The Event-B design pattern is an excellent way to quickly develop a formal model of the system. Researchers have proposed a number of Event-B design patterns, but they all lack formal behavior semantics. This makes the analysis, verification, and simulation of the behavior of the Event-B model very difficult, especially for the control-intensive systems. In this paper, we propose a novel method to transform the Event-B synchronous control flow design pattern into the labeled transition system (LTS) behavior model. Then we map the design pattern instantiation process of Event-B to the instantiation process of LTS model and get the LTS behavior semantic model of Event-B model of a multi-level complex control system. Finally, we verify the linear temporal logic behavior properties of the LTS model. The experimental results show that the analysis and simulation of system behavior become easier and the verification of the behavior properties of the system become convenient after the Event-B model is converted to the LTS model.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.633-640
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• 2007

As the embedded systems closely related with our living become complex by interoperating each other via internet, the safety issue of embedded systems begins to appear For checking safety properties of the system interactions, it is necessary to describe the system behaviors in formal methods and provide a systematic safety analysis technique. In this research, the behaviors of an embedded system are described by Labeled Transition Systems(LTS) and its safety properties are checked on the system model. For enhancing the existing compositional safety analysis technique, we perform the safety analysis techniques by checking the behavioral equivalence of the reduced model and a property model after reducing the system model in the viewpoint of the property.

• Journal of KIISE:Software and Applications
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• v.35 no.9
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• pp.529-537
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• 2008

Since concurrent software is hard to debug, the verification of such systems inevitably needs automatic tools which support exhaustive searching. Bounded Model Checking (BMC) is one of them. Within a bound k, BMC exhaustively check some errors in execution traces of the given system. In this paper, we introduce the tool that performs BMC for LTS, modeling language for concurrent programs. In this tool, a property is described by a FLTL formula, which is suitable to present the property with actions in a LTS model. To experiment with existential model checkers and out tool, we compare and analysis the performance of the developed tool and others.

• Proceedings of the KSR Conference
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• 2003.10c
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• pp.581-586
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• 2003

As a very important part in development of the protocol, verification and conformance test for protocol specification are complementary techniques that are used to increase the level of confidence in the system functions. as prescribed by their specifications. In this paper, we verify the safety and liveness properties of rail signal control protocol type 1 specified in LTS(Labeled Transition System) with model checking method, and experimentally prove that it is possible to check for the deadlock, livelock and rechability of the states and actions on LTS. We also propose a formal method on generation of conformance test cases using the concept of UIO sequences from verified protocol specification.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.454-457
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• 2003

대규모 시스템 명세의 올바름을 검증하기 위한 유한상태 LTS(Labeled Transition System)에 기반을 둔 CTL(Computation Tree Logic) 논리 적용의 문제점은 시스템 내부의 병렬 프로세스간 상호 작용으로 인한 상태폭발이다. 그러나 medal mu-calculus 논리를 시스템 안전성 및 필연성 특성 명세에 사용하면, 행위에 의한 순환적 정의가 가능하므로 상태폭발 문제가 해결된다. 본 논문에서는 LTS 로 명세화 된 철도 신호제어용 프로토콜 모델의 안전성 및 필연성 특성을 모형 검사 기법에 의해 검증하기 위해 시제 논리로 사용된 modal mu-calculus를 사용하여 해당 검정 알고리즘을 구현 및 적용하였다.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.358-362
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• 2004

Verification and testing are complementary techniques that are used to increase the level of confidence in the correct functioning of communication systems as prescribed by their specifications. This paper presents an experience of model checking for a formal railway signaling protocol specified in LTS (Labeled Transition System). This formal approach checks deadlock, livelock and reachability for the state and action to verify whether properties expressed in modal logic are true on specifications. We also propose a formal method for semi-automated test case generation for a railway signaling protocol described in I/O FSM (Input/Output Finite State Machine). This enables the generation of more complete and consistent test sequence for conformance testing. The above functions are implemented by C++ language and included within RSPVTE (Railway Signaling Protocol Verification and Testing Environment).

• Proceedings of the KSR Conference
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• 2004.06a
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• pp.1452-1455
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• 2004

In this paper, we develope a protocol verification tool that verifies the correctness of rail signal control protocol type 2 specified in LTS(Labeled Transition System) by using model checking method. This tool automatically checks several properties for deadlock, livelock and reachability of states and actions on LTS. and removes many errors and ambiguities of an informal method used in the past, so saves down expenditures and times required in the protocol development. Therefore it is expected that there will be an increase in safety, reliability and efficiency in terms of the maintenance of the signaling system by using the developed verification tool.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.354-357
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• 2004

According to the computerization of railway signaling systems, the interface link between the signaling systems has been replaced by the digital communication channel. At the same time, the importance of the communication link is more pronounced than in the past. In this paper, new network-based protocol for Korean railway signaling has designed between CTC and SCADA system, and the overview of designed protocol is briefly represented. Using the informal method for specifying the communication protocol, a little ambiguity may be contained in the protocol. To clear the ambiguity contained in the designed protocol, we use LTS model to design the protocol for this interface link between CTC and SCADA, the LTS is an intermediate model for encoding the operational behavior of processes. And then, we verify automatically and formally the safety and the liveness properties through the model checking method. Especially, the modal ${\mu}$-calculus, which is a highly expressive method of temporal logic that has been applied to the model checking method. It will be expected to increase the safety, reliability and efficiency of maintenance of the signaling systems by using the designed protocol for railway signaling in Korea.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.513-519
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• 2006

As a very important part in development of the protocol, verifications for developed protocol specification are complementary techniques that are used to increase the level of confidence in the system functions by their specifications. Using the informal method for specifying the protocol, some ambiguity may be contained therein. This indwelling ambiguity in control systems can cause the occurrence of accidents, especially in the case of safety-critical systems. To clear the vagueness contained in the designed protocol, we use the LTS (Labeled Transition System) model to design the protocol for railway signaling. And then, we verify the safety and the liveness properties formally through the model checking method. The modal ${\mu}$-calculus, which is an expressive method of temporal logic, has been applied to the model checking method. We verify the safety and liveness properties of Korean standard protocol for railway signaling systems. To perform automatic verification of the safety and liveness properties of the designed protocol, a communication verification tool is implemented. The developed tools are implemented by C++ language under Windows XP. It is expected to increase the safety and reliability of communication protocol for signaling systems by using the developed communication verification tool.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1119-1133
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• 2005

As a very important part in development of the protocol, verification and conformance test for protocol specification are complementary techniques that are used to increase the level of confidence in the system functions as prescribed by their specifications. In this paper, we verify the safety and liveness properties of rail signal control protocol type 1 specified in LTS with model checking method, and experimentally prove that it is possible to check for the deadlock, livelock and rechability of the states and actions on LTS. The implemented formal checker is able to verify whether properties expressed in modal logic are true in specifications using modal mu-calculus. We also propose a formal method on generation of conformance test cases using the concept of UIO sequences from verified protocol specification. The suggested tools are implemented by C++ language under Windows NT.