• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.78-84
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• 2012

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.35-44
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• 2003

The effectiveness of buffer cache replacement algorithms is critical to the performance of I/O systems. In this paper, we propose the degree of inter-reference gap (DIG) based block replacement scheme that retains merits of the least recently used (LRU) such as simple implementation and good cache hit ratio (CHR) for general patterns of references, and improves CHR further. In the proposed scheme, cache blocks with low DIGs are distinguished from blocks with high DIGs and the replacement block is selected among high DIGs blocks as done in the low inter-reference recency set (LIRS) scheme. Thus, by having the effect of the partitioning the cache memory dynamically based on DIGs, CHR is improved. Trace-driven simulation is employed to verified the superiority of the DIG based scheme and shows that the performance improves up to about 175% compared to the LRU scheme and 3% compared to the LIRS scheme for the same traces.

• The KIPS Transactions:PartC
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• v.9C no.6
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• pp.961-968
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• 2002

This paper proposes a new access method which is to considered the high variability in World Wide Web and manage the web cache space. Instead of using a single cache, we divide a cache and store all documents according to their file types. Proposed method was compares with current cache management policies using LFU, LRU and SIZE base algorithm. Using two different workload, we show the improvement hitting ratio and byte hitting ratio through simulating on the file type caching.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.10-12
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• 2001

웹에서 도큐먼트 재배치 정책은 캐쉬(cache)성능을 향상시키기 위한 방법중의 하나이다. 이 방법을 웹 캐쉬 공간이 한정되어 있으며 새로운 도큐먼트를 위한 공간을 만들기 위해 어느 도큐먼트를 축출(remove)[2]할 것인가를 결정하고 새로운 도큐먼트를 갱신(update)[6]하기 위한 방법을 제공한다. 도큐먼트 재배치 정책으로는 LRU(Least Recently Used), LFU(Least Frequently Used)등과 같은 방법이 보편적을 사용되고 있으나, 웹에 적용하기에는 몇 가지 단점이 있다. 본 논문에서는 LRU, LFU등의 도큐먼트 재배치 정책을 이용하면서도 웹에 적용하기 위해 몇 가지 단점을 보완한 LRFU(Least Recently/Frequently Used)[4]기법을 사용한다. 또한 본 논문에서는 인터넷(internet) 사용자의 지수적인(exponential) 증가와 이로 인한 병목현상(bottleneck)의 발생을 전제로 하여, 캐쉬성능을 향상시키기 위한 다각적인 시도로 지역성(locality), 일관성(consistency)[7][5], 확장성(scalability)[5]등의 문제에 관한 논의와 기존의 방법과는 다른 도큐먼트 재배치 정책에의 접근을 시도한다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.112-114
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• 2004

무선 통신 기술의 발달로 인하여 LBS(Location Based System)와 같은 새로운 이동체 관련 서비스가 생겨나고 있다. 위치 기반 서비스에서 클라이언트인 이동체들이 주기적으로 보고하는 위치 데이터를 실시간으로 처리하기 위해 서버에서는 메인 메모리 DBMS를 유지하는 것이 필요한데, 데이터의 양이 계속적으로 증가하는 특성으로 인해 메인 메모리의 공간이 부족할 때 데이터를 디스크로 옮기는 시스템 설계가 필요하다. 그러나 기존의 연구는 대용량 이동체 환경에서의 색인 이주를 위한 노드 선택 정책과 이주를 위해 선택된 노드들의 디스크 배치 정책을 통합하여 나타내지 못하였다. 그러므로 대용량 이동체 데이터베이스 시스템 환경에 적합한 이주 정책들에 대한 연구가 필요하다. 이 논문에서는 대용량 이동체 데이터베이스 환경을 고려한 노드 선택 정책과 디스크 배치 정책을 분류하고 새로운 이주 정 책을 제시한다. 노드 선택 정책으로는 질의 성능을 위해서 캐쉬의 LRU(Least Recently Used) 정책을 이용한 변형된 LRU정책을 제시하고, 삽입 우선 정책으로는 이동체 색인인 R-tree의 삽입 알고리즘을 역이용한 정책을 제시한다. 또한 이주되는 노드들에 대한 디스크 페이지 배치가 시스템의 질의 성능에 영향을 미치므로 이를 고려한 디스크 배치 정책을 제시한다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.8
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• pp.621-629
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• 2020

LRU layout is a complex problem that requires consideration of various criteria such as airworthiness, performance, maintainability and environmental requirements. As aircraft functions become more complex, the necessary equipment is increasing, and unmanned aerial vehicles are equipped with more equipment as a substitute for pilots. Due to the complexity of the problem, the increase in the number of equipment, and the limited development period, the placement of equipment is largely dependent on the engineer's insight and experience. For optimization, quantitative criteria are required for evaluation, but criteria such as safety, performance, and maintainability are difficult to quantitatively compare or have limitations. In this study, we consider the installation and maintenance of the equipment, simplify the deployment model to the traveling salesman problem, Optimization was performed using a genetic algorithm to minimize the weight of the connecting cable between the equipment. When the optimization results were compared with the global calculations, the same results were obtained with less time required, and the improvement was compared with the heuristic.

• Journal of Korea Multimedia Society
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• v.10 no.5
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• pp.583-593
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• 2007

We study the page replacement algorithms for demand paging, called CFLRU/C, CFLRU/E and DL-CFLRU/E, that reduce the number of erase operations and improve the wear-leveling degree of flash memory. Under the CFLRU/C and CFLRU/E algorithms, the victim page is the least recently used dean page within the pre-specified window. However, when there is not any dean page within the window, the CFLRU/C evicts the dirty page with the lowest frequency while the CFLRU/E evicts the dirty page with the highest number of erase operations. The DL-CFLRU/E algorithm maintains two page lists called the dean page list and the dirty page list, and first finds the page within the dean page list when it selects a victim. However, when it can not find any dean page within the dean page list, it evicts the dirty page with the highest number of erase operations within the window of the dirty page list. In this thesis, we show through simulation that the proposed schemes reduce the number of erase operations and improve the wear-leveling than the existing schemes like LRU.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.6
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• pp.119-124
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• 2023

This paper proposes a new reference model that can represent data access with temporal locality and popularity bias. Among existing reference models, the LRU-stack model can express temporal locality, which is a characteristic that the more recently referenced data has, the higher the probability of being referenced again. However, it cannot take into account differences in popularity of the data. Conversely, the independent reference model can reflect the different popularity of data, but has the limitation of not being able to model changes in data reference trends over time. The reference model presented in this paper overcomes the limitations of these two models and has the feature of reflecting both the popularity bias of data and their changes over time. This paper also examines the relationship between the cache replacement algorithm and the reference model, and shows the optimality of the proposed model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1167-1175
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• 2016

This paper proposes an efficient page-level mapping algorithm that reduces the erase count in the FTL for flash memory systems. By maintaining the weight for each write request in the request buffer, the proposed algorithm estimates the degree of temporal locality for each incoming write request. To exploit temporal locality deliberately for determination of hot request, the degree of temporal locality should be much higher than the reference point determined experimentally. While previous LRU algorithm treats a new write request to have high temporal locality, the proposed algorithm allows write requests that are estimated to have high temporal locality to access hot blocks to store hot data intensively. The pages are more frequently updated in hot blocks than warm blocks. A hot block that has most of invalid pages is always selected as victim block at Garbage Collection, which results in delayed erase operation and in reduced erase count. Experimental results show that erase count is reduced by 9.3% for real I/O workloads, when compared to the previous LRU algorithm.

• Journal of the Korea Society of Computer and Information
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• v.18 no.12
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• pp.1-9
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• 2013

Even though the multiple pages TLB are effective in improving the performance, a conventional method with OS support cannot utilize multiple page sizes in user application. Thus, we propose a new multiple-TLB structure supporting multiple page sizes for high performance and low power consumption without any operating system support. The proposed TLB is organised as two parts of a S-TLB(Small TLB) with a small page size and a L-TLB(Large TLB) with a large page size. Both are designed as fully associative bank structures. The S-TLB stores small pages are evicted from the L-TLB, and the L-TLB stores large pages including a small page generated by the CPU. Each one bank module of S-TLB and L-TLB can be selectively accessed base on particular one and two bits of the virtual address generated from CPU, respectively. Energy savings are achieved by reducing the number of entries accessed at a time. Also, this paper proposed the simple 1-bit LRU policy to improve the performance. The proposed LRU policy can present recently referenced block by using an additional one bit of each entry on TLBs. This method can simply select a least recently used page from the L-TLB. According to the simulation results, the proposed TLB can reduce Energy * Delay by about 76%, 57%, and 6% compared with a fully associative TLB, a ARM TLB, and a Dual TLB, respectively.