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http://dx.doi.org/10.7840/kics.2016.41.10.1167

An Efficient Page-Level Mapping Algorithm for Handling Write Requests in the Flash Translation Layer by Exploiting Temporal Locality  

Li, Hai-Long (Sogang University Department of Electronic Engineering)
Hwang, Sun-Young (Sogang University Department of Electronic Engineering)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.41, no.10, 2016 , pp. 1167-1175 More about this Journal
Abstract
This paper proposes an efficient page-level mapping algorithm that reduces the erase count in the FTL for flash memory systems. By maintaining the weight for each write request in the request buffer, the proposed algorithm estimates the degree of temporal locality for each incoming write request. To exploit temporal locality deliberately for determination of hot request, the degree of temporal locality should be much higher than the reference point determined experimentally. While previous LRU algorithm treats a new write request to have high temporal locality, the proposed algorithm allows write requests that are estimated to have high temporal locality to access hot blocks to store hot data intensively. The pages are more frequently updated in hot blocks than warm blocks. A hot block that has most of invalid pages is always selected as victim block at Garbage Collection, which results in delayed erase operation and in reduced erase count. Experimental results show that erase count is reduced by 9.3% for real I/O workloads, when compared to the previous LRU algorithm.
Keywords
NAND flash memory; FTL; Page-level mapping; Temporal locality; Random request;
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Times Cited By KSCI : 3  (Citation Analysis)
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1 Intel Corporation, OLTP Performance Comparison: Solid state Drives vs. Hard Disk Drives, Retrieved Jan. 2009, from http://www.principledtechnologies.com/Inetel/OLTPSSDPerf0109.pdf.
2 S. Lee, B. Moon, and C. Park, "Advances in flash memory SSD technology for enterprise database applications," in Proc. Management of Data Conf., pp. 863-870, New York, NY, Jun. 2009.
3 D. Ma, J. Feng, and G. Li, "A survey of address translation technologies for flash memories," ACM Computing Surveys, vol. 46, no. 3, Article 36, Jan. 2014.
4 S. Lee and H. Bahn, "Characterizing memory references for smartphone applications and its implications," J. Semiconductor Technol. Sci., vol. 15, no. 2, Apr. 2015.
5 Q. Wei, et al., "Z-MAP: A zone-based flash translation layer with workload classification for solid-state drive," ACM Trans. Storage, vol. 11, no. 1, Article 4, Feb. 2015.
6 J. Hsieh, T. Kuo, and L. Chang, "Efficient identification of hot data for flash memory storage systems," ACM Trans. Storage, vol. 2, no. 1, pp. 22-40, Feb. 2006.   DOI
7 J. Kim, et al., "A space-efficient flash translation layer for compactflash systems," IEEE Trans. Consumer Electron., vol. 48, no. 2, pp. 366-375, May 2002.   DOI
8 A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings," in Proc. Architectural Support for Program. Lang. Operating Syst. Conf., pp. 229-240, New York, NY, Mar. 2009.
9 D. Kim and S. Hwang, "An efficient wear-leveling algorithm for NAND flash SSD with multi-channel and multi-way architecture," J. KICS, vol. 39B, no. 7, pp. 425-432, Jul. 2014.   DOI
10 L. Chang, Y. Liu, and W. Lin, "Stable greedy: Adaptive garbage collection for durable page-mapping multichannel SSDs," ACM Trans. Embed. Comput. Syst., vol. 15, no. 13, Article 13, Jan. 2016.
11 S. Choe, H. Cho, and T. Chung, "Garbage collection-centric FTL for improving the processing delay of flash memory," J. KIISE, vol. 40, no. 4, pp. 181-192, Aug. 2013.
12 J. Kang, et al., "A superblock-based flash translation layer for NAND flash memory," in Proc. Embedded software Conf., pp. 161-170, New York, NY, Oct. 2006.
13 S. Lee, et al., "LAST: Locality-aware sector translation for NAND flash memory-based storage systems," ACM SIGOPS Operating Syst. Rev., vol. 42, no. 6, pp. 36-42, Oct. 2008.   DOI
14 R. Karedla, J. Love, and B. Wherry, "Caching strategies to improve disk system performance," IEEE Comput., vol. 27, no. 3, pp. 38-46, Mar. 1994.
15 S. Leutenegger and D. Dias, "A modeling study of the TPC-C benchmark," in Proc. Management Data Conf., pp. 22-31, New York, NY, Jun. 1993.
16 N. Agrawal, et al., "Design tradeoffs for SSD performance," in Proc. USENIX Technical Conf., Berkeley, CA, Jun. 2008.
17 S. Lim, S. Lee, and B. Moon, "FASTer FTL for enterprise-class flash memory SSDs," in Proc. Storage Netw. Architecture and Parallel I/Os, Ipp. 3-12, ncline Village, NV, Sept. 2010.
18 OLTP and Web Search Traces from Umass Trace Repository, http://traces.cs.umass.edu/index.php/Storage/Storage.
19 The DiskSim Simulation Environment Version 3.0 Reference Manual, CMU, Jan. 2003.
20 Y. Kim, B. Tauras, A. Gupta, and B. Urgaonkar, "FlashSim: A simulator for NAND flash-based solid-state drives," in Proc. Advances in Syst. Simulation Conf., pp. 125-131, Porto, Portugal, Sept. 2009.
21 Block I/O Traces from IOTTA Repository, http://iotta.snia.org/tracetypes/3.