• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.1
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• pp.139-146
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• 2003

In this paper we demonstrate a cryptanalysis of the stream cipher LILI-128. Our approach to analysis on LILI-128 is to solve an overdefined system of multivariate equations. The LILI-128 keystream generato $r^{[8]}$ is a LFSR-based synchronous stream cipher with 128 bit key. This cipher consists of two parts, “CLOCK CONTROL”, pan and “DATA GENERATION”, part. We focus on the “DATA GENERATION”part. This part uses the function $f_d$. that satisfies the third order of correlation immunity, high nonlinearity and balancedness. But, this function does not have highly nonlinear order(i.e. high degree in its algebraic normal form). We use this property of the function $f_d$. We reduced the problem of recovering the secret key of LILI-128 to the problem of solving a largely overdefined system of multivariate equations of degree K=6. In our best version of the XL-based cryptanalysis we have the parameter D=7. Our fastest cryptanalysis of LILI-128 requires $2^{110.7}$ CPU clocks. This complexity can be achieved using only $2^{26.3}$ keystream bits.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05c
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• pp.1953-1956
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• 2003

차세대 Mobil 무선 통신에 적용 가능한 LILI-128 암호의 개선에 대해서 논의한다. 이동통신 단말기처럼 음성 신호를 고속으로 변환하여 전달할 때는 스트림 암호와 블록 암호가 주로 적용되는데, 특히 고속 무선 통신에서는 스트림 암호가 유리하다. 본 논문에서는 유럽 지역 NESSIE 차세대 암호 후보로 제안된 바 있는 LILI-128의 약점을 보완하여 LILI-256 키수열 발생기로 개선하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.363-366
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• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2001.05a
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• pp.77-83
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• 2001

In recent years, the AES in North America and the NESSIE project in Europe have been in progress. Six proposals have been submitted to the NESSIE project including the LILI-128 by Simpson in Australia in the synchronous stream cipher category. These proposals tend towards a design with parallelism of the algorithms in order to facilitate speed-up. In this paper, we consider the PS-LFSR and propose the effective implementation of various nonlinear combiners: memoryless-nonlinear combiner, memory-nonlinear combiner, nonlinear filter function, and clock-controlled function. Finally, we propose m-parallel SUM-BSG and LILI-l28's parallel implementation as examples, and we determine their securities and performances.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.301-309
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• 2002

In this paper, we propose the effective implementation of various nonlinear combiners using by PS-LFSR: m-parallel memoryless-nonlinear combiner, m-parallel memory-nonlinear combiner, m-parallel nonlinear filter function, and m-parallel clock-controlled function. Finally, we propose m-parallel LILI-128 stream cipher as an example of the parallel implementation, and we determine its cryptographic security and performance.

• Journal of Information Technology Services
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• v.17 no.2
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• pp.111-128
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• 2018

About 3.9 million apps and 24 primary categories can be approved on Apple iTunes Store. Making accurate categorization can potentially receive many benefits for developers, app stores, and users, such as improving discoverability and receiving long-term revenue. However, current categorization problems may cause usage inefficiency and confusion, especially for cross-attribution, etc. This study focused on evaluating the reliability of app categorization on Apple iTunes Store by using several rounds of inter-rater reliability statistics, locating categorization problems based on Machine Learning, and making more accurate suggestions about representative functionality stems for each primary category. A mixed methods research was performed and total 4905 popular apps were observed. The original categorization was proved to be substantial reliable but need further improvement. The representative functionality stems for each category were identified. This paper may provide some fusion research experience and methodological suggestions in categorization research field and improve app store's categorization in discoverability.