• 제어로봇시스템학회논문지
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• 제7권11호
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• pp.939-943
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• 2001

PLC(programmable Logic Controller)s essential components of modern automation systems encompassing almost every industry. Ladder Diagrams (LD) have been widely used in the design of such PLC since the LD is suitable for the modeling of the sequential control system. However, the synthesis of LD itself mainly depends on the experience of the industrial engineer, which may results in unstructured or inflexible design. Hence, in this paper, we propose a ladder diagram conversion algorithm which systematically produces LDs for PLCs based on discrete event models to enhance the structured and flexible design mechanism.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.124.4-124
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• 2001

It needs a skillful experience to design and implement sequential circuits with a relay circuit or LD (Ladder Diagram). One makes out the operation of relay contacts sequentially in case of analyzing a relay circuit or LD. Still more, the design and analyzing of a complex relay circuit or LD are difficult. In this paper, we propose the EMFG (Extended Mark Graph) representation on relay circuits and LD.

• 한국정보과학회논문지:소프트웨어및응용
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• 제37권1호
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• pp.54-59
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• 2010

산업자동화 분야에는 특수목적 마이크로콘트롤러인 PLC가 널리 사용된다. PLC 프로그램 분석과 검증을 위한 연구에서 우선적으로 해야 할 일은 PLC 프로그래밍 언어의 의미구조를 정형적으로 제시하는 것이다. 본 논문은 PLC 프로그래밍에 널리 사용하는 LD 언어의 의미구조를 정의한다. LD 언어는 그래픽 언어이기 때문에 먼저 텍스트 언어 Symbolic LD로 구문구조를 정형화한 다음에, Symbolic LD에 대한 의미구조를 정의할 수가 있다. 본 논문은 Symbolic LD의 의미구조를 자연 의미구조 기법으로 정의하고, 증명 보조기 Coq을 이용하여 정형화하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 B
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• pp.699-702
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• 1999

This paper represents the application of a virtual plant simulator and a Ladder Diagram of PLC. A target plant is a material transport car that repeatedly conveys along the rails. The whole process is automatically operated by PLC. The simulation system consists of the POSFA PLC and the virtual plant simulator. We demonstrate that operation of a LD program corresponds to operation of the virtual plant simulator.

• 제어로봇시스템학회논문지
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• 제5권1호
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• pp.33-38
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• 1999

This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

• 조명전기설비학회논문지
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• 제20권4호
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• pp.49-55
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• 2006

PLC를 사용한 공정제어에서 일반적으로 LD 언어로 가장 많이 프로그램한다. 그러나 최근에는 SFC 언어에 대한 연구가 활발히 이루어지고 있다. PLC를 사용한 공정제어에서 SFC 언어로 프로그램할 때는 처음부터 마지막까지 하나의 루틴으로 설계하는 것이 일반적이다. 이러한 방법은 설계하기가 무척 힘들고, 흔히 실수하는 경우가 많다. 본 논문에서는 개별 서브시스템을 설계하고, 각 서브시스템을 결합하는 방법을 제안하였고, 실례를 통해 그의 타당성을 확인하였다.

• 제어로봇시스템학회논문지
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• 제8권5호
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• pp.401-406
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• 2002

As product lifecycles become shorter, factories are pushed to develop small batches of many different products. The highly flexible control systems has become a necessity. The majority of existing automated industrial systems are controlled by programmable logic controllers(PLCs). In most cases, the control programs for PLCs are developed based on ladder diagrams(LDs). However, it is difficult to debug and maintain those LDs because the synthesis of LD itself mainly depends on the experience of the industrial engineer via trial-and-error methods. Hence, in this paper, we propose a discrete event model conversion algorithm for systematic analysis of LDs. The proposed discrete event model conversion algorithm is illustrated by an example of a conveyor system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.273-275
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• 2006

Ladder Diagram(LD) is the most widely utilized among many sorts of existing programs using for the design of process control system. But it is very difficult to grasp sequential flow of control logic. In this paper, we proposed the method that we can control a lot of blocks. We used PLC in process control system. And, in order to design we used Sequential Function Chart(SFC). In this paper, we proposed the method of block contro. and confirmed feasibility through a simulation.

• 조명전기설비학회논문지
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• 제19권3호
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• pp.127-133
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• 2005

PLC는 산업용 제어시스템에서 가장 많이 사용되며, 중요한 역할을 하고 있다. 이러한 PLC에서 사용되는 언어에 대한 연구도 활발히 이루어지고 있다. PLC에서는 LD언어가 가장 많이 사용되고 있다. LD언어는 데이터의 흐름을 알 수 없고, 유지보수가 어렵다. 반면에 SFC는 제어의 흐름을 이해하기 쉽고 유지보수가 용이하지만 조건과 인터록 기술에 문제점이 있다. 본 논문에서는 매니지먼트 스텝을 사용한 인터록의 기술에 대한 방법을 제안하였고, 실례를 통해 그의 타당성을 확인하였다.

• 제어로봇시스템학회논문지
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• 제8권8호
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• pp.706-712
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• 2002

In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.