• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.1959-1960
• /
• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.