• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.1-9
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• 2004

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations using a binary method, while division and inversion can be performed by the iterative application of an AB$^2$ operation. Hence, it is important to develop a fast algorithm and efficient hardware for this operations. In this paper presents new bit-serial architectures for the simultaneous computation of multiplication and squaring operations, and the computation of an $AB^2$ operation over $GF(2^m)$ generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the Proposed architectures include regularity and modularity, they can be easily designed on VLSI hardware and used in IC cards.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.8-15
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• 2007

This paper proposed hardware architecture of the block cryptographic algorithm HIGHT aiming small size and low power application, and analyzed its performance. The HIGHT is a modified algorithm of the Feistel. The encryption and decryption circuit were designed as one iterative block. It reduces the redundant circuit that yields small area. For the performance improvement, the circuit generates 32-bit subkey during 1 clock cycle. we synthesized the HIGHT with Hynix $0.25-{\mu}m$ CMOS technology. The proposed circuit size was 2.658 EG(equivalent gate), and its power consumption was $10.88{\mu}W$ at 2.5V for 100kHz. It is useful for a passive RFID tag or a smart IC card of a small size and low power.

• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.6
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• pp.779-785
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• 2012

In this paper, we have analyzed the curvature effects of the finite FSS(frequency selective surface) using the 3-D method of moment using the BiCGSTab algorithm as an iterative method. To validate the analysis method in this paper, we compared the RCS(radar cross section) of PEC(perfect electric conductor) sphere with theoretical results and it shows well agreements. The tripole slot FSSs which have many application in military were selected for the investigation of curvature effect and RCS as a frequency characteristics were observed with the variation of the curvature rate. Simulation results shows that curvature effect can significant effect the passband frequency and bandwidth of FSS. We suggest that the curvature effect must be considered at the stage of design FSS application like FSS radome.

• Journal of IKEEE
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• v.16 no.4
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• pp.328-334
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• 2012

In this paper, we analyzed the electromagnetic characteristics of the spherical frequency selective surface with different arrangement of crossed dipole slot elements for reducing the RCS(radar cross section). The three dimensional MOM(method of moment) with RWG basis is used to analyze the proposed structure. To reduce the simulation time, we applied the BiCGSTab(Biconjugate Gradient Stabilized) algorithm as an iterative method and presented the comparison results with Mie's theoretical results for PEC sphere to show the validity of this paper. From the simulation results, the different arrangement of elements array showed the difference RCS that cannot be negligible. The arrangement method of element in frequency selective surface will be one of variables for the design of curved frequency selective structures.